EEL6323-S09-EXAM-R2-SOL

EEL6323-S09-EXAM-R2-SOL - Spring 2009 EEL 6323 Midterm Exam...

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Unformatted text preview: Spring 2009 EEL 6323 Midterm Exam (Closed book, closed notes, 60 Minutes) Name: $91,017 013$ UFID: Problem 1 30 pts. Problem 2 30 pts. Problem 3 40 pts. Total : Honor Code: We, the members of the University of Florida community, pledge to hold ourselves and our peers to the highest standards of honesty and integrity. Signature PROBLEM I — short answer questions (30pts) 1.1 Determine VOUT for each of the circuits below in terms of VDD, VTN and VTp, where VDD is the supply voltage, VTN and VTp are the nMOS and pMOS threshold voltage drops, respectively. Neglect the body effect in each case and assume VDD is at least 5 times larger than the threshold voltages. a.VOUT= 0 b-Vour= 2 [Vltpl C~VOUT: {Vrbpl d VOUT: VDD— Vm VDD VDD VOUT W (a) (b) 6:3 Vino V l (c) M (d) LLJ—r—L Vow E $ 1.2.Which of the following transistors, MA or MB, will exhibit a higher threshold voltage? Justify youranswer. V V MB W1 W2 9% awn-’95» 704 cm (/6 W» ’3‘ PW g. j x 1AM game» WI? c 0/84) m. ta V95 MA MB (b) (a) 1.3.Estimate the gate oxide thickness for a transistor in 250nm and 180nm CMOS technologies. L X6) : %5‘ 1,50 rt M 250 nm TW’”?7 >9 = 4; :‘ 5.514”: I90 run TM X5; .: L944?" iamm 1.4. Threshold voltage for nMOS tran31stor decreases With (select all that apply): \/ a. increase in temperature \/ b. increase in body potential relative to the source 1/ c increase in drain potential relative to the source wed decrease in substrate doping e. increase in oxide thickness 1.5.Find the logical effort of a 2-input NAND gate if they are designed with equal rising and falling delays. Assume a unit size pMOS has 3 times the effective resistance as a unit size nMOS transistor. 4] 3 I 5 Vii 3 A _,.... ail! A ‘ Clh: 5’ 3= %. 1.6. Assume 1 billion transistor chip in 1.0 V 90mm process has 20% of logic transistors with an average width of 107» and 80% of memory transistors with average width of 4)». Furthermore, assume a gate capacitance of Cg = 2 fF/um, an activity factor = 0.1 for Static CMOS logic gates and an activity factor = 0.05 for memory arrays. Estimate dynamic power consumption per MHZ. Neglect wire capacitance and short-circuit current. )\ ; @05er Ca?» = C IXto7X2ofl)- ( 10X) - (0‘05W/A) . sz/um 22mm}; CW -; C (Xafi )(Qv70) - ( 4X). (o‘OSwfi/A‘) « 2&F/W ;: 32/0 n'F- p017“ ; (o_()(m + 0.05x3n) )((I«0)2‘]L- 2,6 mat/fling; H PROBLEM 2 — gate sizing (30pts) Calculate the minimum delay, in terms of 1:, to compute F=AB+CD using: (1) 2 input NAND gates and (2) a compound gate followed by an inverter. In both cases, the input can present a maximum of 20C, where C is the capacitance associated with a unit sized transistor. Assume a unit size pMOS has 2 times the effective resistance as a unit size nMOS transistor. The output must drive a load equivalent to 100C. Draw the circuit and choose transistor sizes to achieve this delay. Which design is faster? Estimate the absolute delay if the circuit is implemented in 250nm CMOS. A B g :1)? ,4. MM: an P/LMS $4 2 W élidti” MIWO‘ M a. W sl‘ze rut/103 W513”. => 3' _, Né ; - = Z G! = f .3 _, 27. 6‘: 2 l , FW 6”“ 0M“! raw [4:43‘3'325 % _—- Fl ZGIBH; é—H F255z‘B-H: (O A A fl ’— 18" =BI6 P(:2+2:4 P114+I;6. DI = 2*2‘76’ +4 : 9.76:. Dz : 2mm“; = ".52.: If th ,‘5 ,mpéeW m 260 nm W05. ® 1 : 27%,0; : I5‘67PS. -‘—> D, =‘ I56 P3 D}: /99 p5 PROBLEM 3 — Path Logical Effort (40pts) The following circuit computes the logical function: if(a = = b) y = 67? else y = 0; Assume a, b and y are 16-bit buses. Assume the input and output capacitances are each 10 units. Your goal is to make the circuit as fast as possible. Estimate the delay in F04 inverter delays using Logical Effort if the best gate sizes were used. What sizes do you need to use to achieve this delay? Y 7* Cé-é%/6)*2 5 : 2,.54 Extra work page ...
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EEL6323-S09-EXAM-R2-SOL - Spring 2009 EEL 6323 Midterm Exam...

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