This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: Spring 2010 EEL 6323 Midterm Exam
(Closed book, closed notes, 60 Minutes) Name: UFID: Problem 1 30 pts.
Problem 2 40 pts.
Problem 3 30 pts.
Total : Honor Code:
We, the members of the University of Florida community, pledge to
hold ourselves and our peers to the higheSt standards of honesty and integrity. Signature Note: Please show work. Answers without analysis will not receive credit. PROBLEM I — short answer questions (30pts) 1.1 List three power reduction techniques employed in VLSI design CD Géoc/é W K? 996% e’% (M5) K3) Mulin WWW 1.2.Pollack’s rule states that the performance increase by microarchitecture alone is roughly
proportional to: (a) 1 x Complexity
(b) 1 x Power Square root of Complexity
d) Square root of Power 1.3.Find the decimal representation of the 4bit 2’s complement number 1001 before and afier a
2 bit arithmetic shift right operation, or ASR2. Beﬁw (00/ —7D.
A756”? 11/0 —.ZD 1.4.Explain the inversion property in adders and specifically how is it useful? Co
A “ FA >5 —> 4 S
g ’— " FA
8
Cc w WW'M 79/12 wit/€01 PM 7 madam? ,Wwﬁv W 1.5.Consider the HLFF shown in Fig. 1.5a below. The designer has sized the transistors and runs
a transient simulation as shown in Fig. 1.5b. Explain why a glitch appears in “Q” after the
rising “Clk” edge. 5 <i:l p/Q
D=High
'\
C/k
glitch
(b) came "Ni
53 W ‘
~ Dot/M3 W (De/UM T, 373wa 'dk“m "CL/(JV Mg 0» WM 159’” 62 a) OCW;‘ Wﬁ/D‘M £2 IW .y /:n PROBLEM 2 (40pts) For the group PG cell symbols shown below: 2.1.Draw the PG diagram ofa 4bit CarrySelect adder with 2 blocks (i.e. M=2, N=4). Use only
the group cells shown below to draw your adder. To receive full credit you will need to
accurately draw the wiring between cells. 2.2.Using the basic rules ofthumb about F04 delay and technology, estimate the critical path
delay ifthis adder were to be implemented in 65nm CMOS technology. Assume that all the gate delays are approximately equivalent to a F04 inverter delay. 2.3.Using the same assumptions as in question 2.2, estimate the worstcase propagation delay of
summing the unsigned binary numbers ll’lO and 0010. PG Logic Generate Logic Sum Logic AND gate MUX pi Gi CH ci 81? D =0— PROBLEM 3: (30 Points) As shown in ﬁgure below, two cases are presented in which waveforms “a” and “b” are applied
to the circuit. Assuming the capacitor CL is initially discharged and the circuit time constant is
very small, we would like to ﬁnd out the energy characteristics at time t1 when the waveforms in
Case 1 and Case 2 are applied: 1. Energy stored on the capacitor CL. 2. Energy dissipated in the switching transistor. ’7 3. Total energy supplied (Note: assume short circuit and static power dissipation is negligible) time
out time Case 1 I Case 2 Fig. P3: Proposed schemes for energy comparison. Own c if , ,1, 2i
D i Eu 5J3, VC'CLof/(i 0% 3/3009C4 VCWLVC ’ 2163/99 7' 2 . V, I r 2
) ’32: EDIE 3 ( VDO'Vc)CL%D{/t :jd”)CLC%U’I/G)Wc ' 2641/” 3) C4. UDD gm : ECL ‘l’ EDI‘S : C4 l/ﬂg' Cat/ye 2 ; VJ M M ‘
t, c , 2 m : _ I
I) I ECL=JO ’ 5a Cl. i/C C 164V” Z
L L _ ( :1!» Von
D 14": Cal/hp ﬁDI‘S sj:(\/b—V¢)‘CL%DL€ Z (EZEP‘ V¢)‘C40W¢+ jg?” (VDD‘VC)CL0(A/c
3) % vaé’p. : Q; Cal/D; em = 593': + Ea,  3
’ Extra work page ...
View
Full Document
 Spring '09
 Guan

Click to edit the document details