EEL6323-S10-EXAM-I-SOL

# EEL6323-S10-EXAM-I-SOL - Spring 2010 EEL 6323 Midterm Exam...

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Unformatted text preview: Spring 2010 EEL 6323 Midterm Exam (Closed book, closed notes, 60 Minutes) Name: UFID: Problem 1 40 pts. Problem 2 30 pts. Problem 3 30 pts. Total : Honor Code: We, the members of the University of Florida community, pledge to hold ourselves and our peers to the highest standards of honesty and integrity. Signature Note: Please Show work. Answers without analysis will not receive credit. PROBLEM 1 (40pts) Short answer questions 1.1. For the transistor networks shown below, determine the logic functions (if any) and the voltage levels at the output of each logic gate. 006T; A98 007:,4c95 1.2 Estimate the frequency ofthe following 13 stage ring oscillator if implemented in 180nm CMOS technology. 1.3 The delay versus fanout for gates A and B are plotted below. Extract the logical effort (g) and parasitic delay (p) for each gate. In addition, give at least one example of gates A and B. EB Normalized Delay: d o 1 2 3 4' 5 3 -‘ N/GNDZ. Electrical Effort: h = C / C. out In 1.4 The DC characteristics of an inverter (X) are deﬁned as VIHX=3.1 volts, VILX=1.8 volts, VOHX=4.5 volts, VOLX=0.9 volts. The DC characteristics of another inverter (Y) are deﬁned as VIHy=2.9 volts, VILy=l .2 volts, VOHY=42 volts, VOLy=0.3 volts. Which of the following conﬁgurations has the largest NMH? Assume Vdd=5 volts. Ga) X drives Y b. Y drives X c. X drives X d. Y drives Y 1.5 Consider both the Verilog-HDL and VHDL RTL descriptions ofa component name “MUX_INV” provided below. The codes are functionally identical to each other. Draw the output waveform of this design given the input signals shown below: Verilog Code VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; module MUX_INV (out, a, b, sel) output out; input a, b, sel; entity MUX_INV is reg out; port ( a : in std_logic; always @(sel) b : in std_logic; begin sel : in std_logic; case (sel) out : out std_logic ); 1’b0: out = la; end MUX_INV; l’bl: out = lb; endcase architecture Behavioral of MUX_INV is end begin endmodule muXProc: process (sel) case sel is when “0" => out <= not a; when “1" => out <= not b; endcase; end process muxProc; end Behavioral; PROBLEM 2: (30 Points) Consider the following simpliﬁed transistor model in Fig. P2.l. In the figure below, k is the transistor multiplier factor, where a large k implies a large transistor width. The transistor resistance Rd equals R/k, where R is some unit resistance. Similarly, the parasitic Source/Drain capacitances CS and Cd equal kC, where C is some unit capacitance. kaC - Fig. P2.1: simplified transistor model With this in mind, estimate the pull down delay of the following two circuits (Fig. P22). Assume the output capacitance CL is initially charged to Vdd and the transistor layout is such that the diffusion regions are NOT overlapped. Moreover, assume that the inputs Inl=InZ=In3=ln4 transition simultaneously from 0 to 1 (i.e. from 0 to Vdd). Which circuit is faster? Justify your work. k1=16 _ k =2 _ "14 M1 I.cL—szc W 1 W I oL—szc k2=8 k2=4 In3 M2 m3 M2 k =4 k =3 In2 3 M3 In2 3 M3 k =2 k =16 mi 4 M4 "‘1 4 M4 Fig. P2.2: Pull down circuits. We“; .. _ R th‘j‘»(2C+4C)X—2‘ + (4C1‘5‘C)X(—§+—\$)+ (86+I6C)XC§+§+§) 'l'C/C-F-l .5 [S K a 6 ZC)X(/é+ 3' +?t:) : 78RC 441% W: fM‘= (/6c+8C)X—/3 + ((§c+--4c)><(--’g 3)1-(4c+2c)x K R k /0/ ’5 8 (“/7 k a +C32C+2C)X(%+-%£+E) a : 38.7E‘Qc => ﬁght we 1': 794a,] PROBLEM 3 (30pts) Select gate sizes x, y and z for least delay from A to B. You will need to consider the critical path (i.e. path with worst case delay). Check your answer. Estimate the absolute delay in 180nm process. >> Asa/mac i yrz :—>F:.221_..3?:3‘96 we .23. i Y =3“ 971:;40 afxm. 2 WW ere—we? elm»; P: 2+2+l+2;7 __ _ l ‘3 = 4.x D ’ (4X45 +7)Z:. zg'Z 5 if S ' 5 _/819X *5— 5+ mm ' —~—~ _ 5 P794055 4-5 ' 7 , /9‘0 i , ;7 Z ' /s’ P9 5 WP: ‘ Y' 44-; :&.2 X z: 8 Lie? \$ D; /2_P5X)4’ 3’3ng 44; Xg : Extra work page ...
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## This note was uploaded on 03/02/2012 for the course ESI 6323 taught by Professor Guan during the Spring '09 term at University of Florida.

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EEL6323-S10-EXAM-I-SOL - Spring 2010 EEL 6323 Midterm Exam...

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