EEL6323-S10-HLec02-CMOSoverview-2spp

EEL6323-S10-HLec02-CMOSoverview-2spp - Homework 1 Find the...

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1 Homework 1 Find the following for 180nm, 130nm, 90nm, 65nm and 45nm CMOS technologies – Effective channel length – Equivalent and physical oxide thickness – Supply voltage (Vdd) Draw the layout for the following Latch (use TSMC 0.25um technology) Due Wed Jan 20, 2009 QM CLK CLK CLK CLK Q CLK CLK CLK CLK D Latch DQ QM CLK CLK Lecture 2: CMOS Overview MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d nMOS g s d s d s d pMOS body/bulk GROUND NMOS/NFET PMOS/PFET channel shorter length, faster transistor (dist. for electrons) body/bulk HIGH positive voltage (Vdd) negative voltage (rel. to body) (GND) (S/D to body is reverse-biased) --- + + + + + + current current MOSFETs as Switches
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2 Complementary MOS Complementary MOS logic gates –nMOS pull-down network –pMOS pull-up network – a.k.a. static CMOS pMOS pull-up network output inputs nMOS pull-down network Pull-down ON Pull-down OFF Pull-up ON Pull-up OFF Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series : – both must be ON Parallel : – either can be ON (a) a b a b g1 g2 0 0 a b 0 1 a b 1 0 a b 1 1 OFF ON (b) a b a b 0 0 a b 0 1 a b 1 0 a b 1 1 (c) a b a b 0 0 (d) O N a b 0 a b 1 a b 1 10 1 a b 0 0 a b 0 a b 1 a b 1 101 a b
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3 Conduction Complement
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EEL6323-S10-HLec02-CMOSoverview-2spp - Homework 1 Find the...

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