EEL6323-S10-HLec03-CMOS-Layout-2spp

EEL6323-S10-HLec03-CMOS-Layout-2spp - 1 Lecture 3: Layout...

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Unformatted text preview: 1 Lecture 3: Layout • CMOS Enhancements • Scalable rules • Poly ordering • Design Partitioning • Floorplanning Layout • Min. feature size expressed in terms of = f /2 – E.g. = 0.3 m in 0.6 m process • Lambda rules are conservative – All dimensions rounded to integer multiple of – Industry employs micron (vendor) rules instead (more compact) Area=money • Why use rules – Easy scaling – Same layout can be resized by scaling • MOSIS (www.mosis.org) – Low cost (relative) fabrication service – Services Academia, industry and government – Shared masks 2 Simplified Design Rules • Conservative rules to get you started Gate Layout • Layout can be very time consuming – Design gates to fit together nicely – Build a library of standard cells • Standard cell design methodology – V DD and GND should abut (standard height) – Adjacent gates should satisfy design rules – nMOS at bottom and pMOS at top – All gates include well and substrate contacts 3 Example: NAND3 • Horizontal N-diffusion and p-diffusion strips • Vertical polysilicon gates • Metal1 V DD rail at top • Metal1 GND rail at bottom • 32 by 40 Standard Cells • Uniform cell height • Uniform well height • M1 V DD and GND rails • M2 Access to I/Os • Well / substrate taps • Exploits regularity 4...
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This note was uploaded on 03/02/2012 for the course ESI 6323 taught by Professor Guan during the Spring '09 term at University of Florida.

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EEL6323-S10-HLec03-CMOS-Layout-2spp - 1 Lecture 3: Layout...

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