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EEL6323-S10-HLec04-DC-Transient-2spp

# EEL6323-S10-HLec04-DC-Transient-2spp - Lecture 4 DC and...

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1 Lecture 4: DC and Transient Analysis DC Analysis Skewed Gates Logic Levels and Noise Margins Transient Response Delay Estimation Reading: Ch. 2 Load Line Analysis For a given V in : –P l o t I dsn , I dsp vs. V out –V out must be where |currents| are equal in E D C B A pMOS nMOS Region I dsn I dsp V out V DD V in I dsn , |I dsp | NMOS PMOS V in5 V in4 V in3 V in2 V in1 V in0 V in1 V in2 V in3 V in4 V out V DD C V out 0 V in V DD V DD AB D E V tn V DD /2 V DD +V tp

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2 Beta Ratio If p / n 1, switching point will move from V DD /2 Other gates: collapse into equivalent inverter VTC depends on how inputs are applied V DD A out W 2W A B out 2W 2W 2W 2W V DD EX: 2-Nand sized for similar WC delay as INV V out 0 V in V DD V DD VTC of complex gates Case 1: one input held HI while other input is switched from Lo-to-HI A=V DD B=0 V DD out 2W 2W 2W 2W V DD V out 0 V in V DD V DD β n / β p = 1
3 VTC of complex gates Case 2: both inputs are switched from Lo-to-HI B=0 V DD out 2W 2W 2W 2W V DD V out 0 V in V DD V DD β n / β p = 1 A=0 V DD VTC of complex gates Case 1: Assume A=0 and B=0 V DD B=0 V DD V out 0 V in V DD V DD β n / β p = 1 A=0 Y 4W 4W W W

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4 VTC of complex gates Case 2: Assume A=0 V DD and B=0 V DD B=0 V DD V out 0 V in V
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