EEL 6323 Advanced VLSI Design - Spring 2011
Instructor: R. Bashirullah
TA: Qiuzhong Wu (
(Due Friday April 27, 2010)
The goal of the project is to study one of the topics specified and design an architecture which consumes
low power, is less sensitive to process variability and occupies as little area as possible. Any of the low
power techniques taught in class (or new ones) can be used when implementing these projects.
LIST OF PROJECTS:
The architecture of the MIPS processor can be taken from the Computer Architecture book written by
David A. Patterson
. The goal of this project is to take the baseline unoptimized
implementation of the MIPS processor given in the book optimize it for power, energy and area. Any of the
power saving techniques can be used. Pipelining and Parallelism can be used. Low power RAMS can be
used. You may even go for a sub- threshold design.
“A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency”
Bo Zhai, Leyla
Nazhandali, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand,Sanjay Pant, David Blaauw
and Todd Austin.
“Low-power CMOS digital design,”
A. Chandrakasan, S. Sheng, and R. Brodersen,
vol. 27, pp. 473–483, Apr. 1992.
“A Leakage Reduction Methodology for Distributed MTCMOS (May, 2004)”,
B. Calhoun, et
al., IEEE Journal of Solid-State Circuits, Vol. 39, No. 5.
”A shared-well dual-supply-voltage 64-bit ALU
”, IEEE Journal of Solid State Circuits. Mar. 2004.
2. FFT Processor
For the FFT project, you must create a hardware implementation of a FFT. The hardware implementation
may be derived from any FFT algorithm (Cooley Tukey or Good Thomas or any other). It can be a radix-2,
radix-4 or any specialized FFT implementations. Achievement of Low power is the main criteria here.
Below are several articles on FFT hardware implementations: