EEL6323-S11-HLec012-Digital-I-4spp

EEL6323-S11-HLec012-Digital-I-4spp - Phases of Design Flow...

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Overview of Digital IC Design Flow Qiuzhong Wu Phases of Design Flow • Phase 1: Design Planning – From application requirements to specifications • Phase 2: Design Implementation and Verification – From SPEC to layout ( GDSII ) • Phase 3: Design Review and Tape-out – Function, timing etc. 2 Phase 1 Tasks • Define Specifications Based on the Application Requirements • HW/SW Partition • Algorithm Design • Architecture Design • Design Partition (Clock, Power etc) • Define the SPEC of Sub-blocks • Effort Estimation and Resources Allocation 3 Phase 2 Tasks • Design Implementation and Verification – Logic design and verification – Physical design and verification • Timing Closure • Power Optimization • Area Refinement 4
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Phase 3 Tasks • Design Review ECO ( Engineering Change Order ) • Tape-out 5 Phase 1: Design Planning Flow chart of Phase 1 7 Specifications • Function Specification • IO Specification • Interface Protocol Specification • Characteristics Specification – Speed –Power –Area 8
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Algorithm Design • Model the system in high-level language –MATLAB –C /C++ –Sys temC – SystemVerilog • Purposes – Understanding of the system – Algorithm design and comparison – Test-Bench and golden files generation 9 Architecture Design • Computation Architecture • Data Path Architecture • Control Path Architecture • Operation Reuse • Clock and Reset Strategy 10 Design Partition • Function Partition • Clock Domain Partition • Power Domain Partition • Full custom design versus standard cell based design 11 Module SPEC Definition • After design partition, the system is divided into separate modules with determinate functions. • Define specification of each module – To carry out implementation in parallel – Design and verification should be done module by module
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Phase 2: Design Implementation Flow Chart of Phase 2 14 RTL Design 15 RTL Coding RTL : Register Transfer Level Verilog-HDL/VHDL (Hardware Description Language) are the two mainstream hardware description languages • Behavior Description VS. Architecture Description module mux_beh(out, a, b, sel) output outp input a, b, sel, assign out=(sel==0)?a:b; endmodule module mux_str(out, a, b, sel) output outp input a, b, sel, not gate1(net1,sel); and gate2(net2, a, net1); and gate3(net3, b, sel); or gate4(out, net2, net3); endmodule 16
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RTL Purification • Find out code defects in RTL level • Make the code more readable and predictable • Assure compatibility with most tools • Find out some possible timing problems in RTL level 17 RTL Code
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This note was uploaded on 03/02/2012 for the course ESI 6323 taught by Professor Guan during the Spring '09 term at University of Florida.

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EEL6323-S11-HLec012-Digital-I-4spp - Phases of Design Flow...

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