EEL6323-S11-HLec013-Digital-II-4spp

EEL6323-S11-HLec013-Digital-II-4spp - Synthesizable RTL...

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RTL Coding and Simulation Synthesizable RTL Coding • When writing RTL, Always think of Hardware ! • Think of Synchronous Hardware – Synchronous design can run smoothly during synthesis, test, simulation, and layout. • Think of RTL , writing in RTL coding style, – register architecture – circuit topology – functionality between registers. HDL Compiler Unsupported •d e l a y initial repeat •w a i t fork event deassign •f o r c e release primitive—User defined primitive •t i m e triand, trior, tri1, tri0, trireg nmos, pmos, cmos, rnmos, rpmos, rcmos pullup, pulldown rtran, tranifo, tranif1,rtranif0,rtranif1 case identity and not identity operators divison and modulus operators – Divison can be done using DesignWare instantiaion Modeling Combinational Logic (1) Types of Combinational Logics Logical / arithmetic equations Logical structure controlling Multiplexers Encoders (Priority encoders) Decoders Comparators ALUs
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Modeling Combinational Logic (2) When modeling combinational logic, the sensitivity list of a process statement (VHDL) or the event list of an always statement (Verilog), must contain all inputs used in the particular statement. If it does not, the model will still synthesize correctly, but may not simulate correctly. This is because process/always statements are concurrent and will not be triggered when the omitted signals change. Example: Multiplexers Symbol S A B Y 00X0 01X1 1X00 1X11 Truth Table A S B Y Gate Level Circuit MUX - RTL Code library IEEE; use IEEE.STD_Logic_1164.all; entity MUX_2_1 is port (Sel, A, B: in std_logic; Y: out std_logic); end MUX_2_1; architecture RTL of MUX_2_1 is begin COMB: process (Sel, A, B) begin if (Sel = ‘1’) then Y <= A; else Y <= B; end if ; end process COMB; end RTL; module MUX_2_1 (Sel, A, B, Y); input Sel, A, B; output Y; reg Y; always @ (Sel or A or B) begin : if (Sel) Y = A; else Y = B; end endmodule Tip 1: Case Statement process (Sel, A, B, C, D) begin case Sel is when “00” Y <= A; when “01” Y <= B; when “10” Y <= C; when “11” Y <= D; end case ; end process ; Using the case statement requires less code and is easier to read when compared with the if statement. This becomes more distinct with increasing numbers of input per output. You can even use for loop statement to handle huge numbers of statements
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Tip 1: Case Statement (cont’d) Guideline : If the priority-encoding is not required, it is recommended to use the case statement rather than if-then-else statement.
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This note was uploaded on 03/02/2012 for the course ESI 6323 taught by Professor Guan during the Spring '09 term at University of Florida.

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EEL6323-S11-HLec013-Digital-II-4spp - Synthesizable RTL...

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