EEL6323-S11-HLec014-Digital-III-4spp

EEL6323-S11-HLec014-Digital-III-4spp - Logic Synthesis...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
Logic Synthesis Logic Synthesis • Logic Synthesis = Translation+ Optimization+ Mapping 2 Gate-Level Optimization 3 Logic Synthesis Flow 4
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Design Compiler Procedure 5 Logic Synthesis Input/Output 6 Design Environment • Beware that the default settings are not realistic conditions. – Input drive is not infinite – Capacitive loading is usually not zero – Consider process, temperature and voltage (PVT) variations. • The operating environment affects the components selected from the target library and timing through your design. • The real world environment your define describe the conditions that the circuit will operate within. 7 Describing Design Environment 8
Background image of page 2
Operating Condition • Operating condition model scales components delay and directs the optimizer to simulate variations in process, temperature and voltage. 9 Design Constraints • Constraints are goals that the synthesizer uses for optimizing a design into a target technology library. • Design rule constraints: technology-specific restriction: – maximum transition – maximum fanout – maximum capacitance • Optimization constraints: design goals and requirements: – maximum delay/minimum delay – maximum area – maximum power 10 Constraint-Driven 11 Technology Dependent 12
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Design Compiler Tutorial (1/5) define_design_lib WORK -path /home/users/guest/VLSI/SYN/WORK analyze -f VHDL /home/users/guest/VLSI/SYN/FSM.vhd elaborate FSM current_design FSM link uniquify current_design FSM create_clock -period 10 Clock set_input_delay -clock Clock 1 SlowRAM set_output_delay -clock Clock 1 {Read Write} compile_dc Design Compiler Tutorial (2/5) compile -ungroup_all -map_effort medium compile -incremental_mapping -map_effort medium
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/02/2012 for the course ESI 6323 taught by Professor Guan during the Spring '09 term at University of Florida.

Page1 / 10

EEL6323-S11-HLec014-Digital-III-4spp - Logic Synthesis...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online