EEL6323-S11-HLec015-Circuit-Families-2spp

EEL6323-S11-HLec015-Circuit-Families-2spp - Lecture 15:...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Lecture 15: Circuit Families Pseudo-nMOS Logic Dynamic, Domino, NP-Domino CVSL, LEAN, CPL Delay What makes a circuit fast? Logical effort is proportional to C/I pMOS are the enemy! Can we take the pMOS capacitance off the input? Various circuit families try to do this… B A 1 1 4 4 Y
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Pseudo-nMOS In the old days, nMOS processes had no pMOS – Instead, use pull-up transistor that is always ON In CMOS, use a pMOS that is always ON 0 0.3 0.6 0.9 1.2 1.5 1.8 0 0.3 0.6 0.9 1.2 1.5 1.8 P = 24 P = 4 P = 14 V in V out V out V in 8/2 P/2 I ds load Sizing Pseudo nMOS Make pMOS about ¼ effective strength of pulldown network 4/3 2/3 A 1 2 AY 0 0.3 0.6 0.9 1.2 1.5 1.8 0 0.3 0.6 0.9 1.2 1.5 1.8 P = 24 P = 4 P = 14 V in V out 8/2 P/2 A
Background image of page 2
3 Logical Effort: Pseudo-nMOS INV The logical effort of each transition is computed as the ratio of the input capacitance to that of a CMOS inverter with equivalent resistance for that transition Inverter 4/3 2/3 A Y g u g d g avg Pull-up Pull-down 1 2 AY 1/3 2/3 g u I P =(2/3)(1/2)I=I/3 R P =IR/(I/3)=3R 4/3 2/3 A Y I N =(4/3)I-(2/3)(1/2)I=I R N =IR/(I)=R g d p u p d p avg Pseudo-nMOS Gates Design for unit current on output to compare with unit inverter. pMOS fights nMOS Inverter NAND2 NOR2 4/3 2/3 A Y 8/3 8/3 2/3 B A Y AB 4/3 4/3 2/3 g u g d g avg p u p d p avg Y g u g d g avg p u p d p avg g u g d g avg p u p d p avg f inputs Y
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Pseudo-nMOS Design Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H G = 1 * 8/9 = 8/9 F = GBH = 8H/9 P = 1 + (4+8k)/9 = (8k+13)/9 N = 2 D = NF 1/N + P = In 1 In k Y Pseudo-nMOS 1 1 H 42 8 1 3 39 Hk Pseudo-nMOS Power Pseudo-nMOS draws power whenever Y = 0 – Static power P = I•V DD
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/02/2012 for the course ESI 6323 taught by Professor Guan during the Spring '09 term at University of Florida.

Page1 / 12

EEL6323-S11-HLec015-Circuit-Families-2spp - Lecture 15:...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online