EEL6323-S11-HLec019-Clock-Distribution-2spp

EEL6323-S11-HLec019-Clock-Distribution-2spp - Lecture 19...

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1 Lecture 19: Clock Distribution Clock distribution trends Distribution networks Clock Power Clock Skew Timing Definitions Source: Ch 7 – J. Rabaey notes, Weste and Harris Notes, S. Russu, ISSCC, Clocking Synchronous systems use a clock to keep operations in sequence Clock must be distributed to all the sequencing elements On practical chips, the RC delay of the wire resistance and gate load is very long – Variations in this delay cause clock to get to different elements at different times –T h i s i s c a l l e d clock skew
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2 Clock definition and parameters Skew Clock Jitter Duty Cycle Variation The clock is a periodic synchronization signal used as a time reference for data transfers in synchronous digital systems [S. Russu. SoC 2004] Clock Distribution Trends [S. Russu. SoC 2004]
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3 Clock Distribution Networks Recall: Buffer Sizing Recall Example: drive 64-bit datapath with unit inverter N= F= f = 1111 84 16 8 2.8 23 64 Initial Driver Datapath Load N: f: D: 1 65 2 8 18 3 4 15 4 2.8 15.3 Fastest 1 2 N 1 f f N C L C IN
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This note was uploaded on 03/02/2012 for the course ESI 6323 taught by Professor Guan during the Spring '09 term at University of Florida.

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EEL6323-S11-HLec019-Clock-Distribution-2spp - Lecture 19...

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