EEL6323-S11-HLec020-Sequencing-2spp

EEL6323-S11-HLec020-Sequencing-2spp - Lecture 20:...

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1 Lecture 20: Sequential Circuits Sequencing Elements Simple Latch/FF Timing Definitions Source: Ch 7 (W&H) Sequencing Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Combinational logic Sequential logic CL clk in out clk clk clk CL CL Pipeline Finite State Machine
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2 Sequencing Elements Latch : Level sensitive – a.k.a. Flip-flop : edge triggered – a.k.a. Timing Diagrams D Flop Latch Q clk clk DQ clk D Q (latch) Q (flop) Latch Design Pass Transistor Latch Pros + + Cons Used in 1970’s
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3 Latch Design Transmission gate + - Inverting buffer + + + DQ D X Q Latch Design Tristate feedback + Buffered input + + Q D X Q D X
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4 Latch Design Buffered output + Widely used in standard cells + Q D X Flip-Flop Design Flip-flop is built as pair of back-to-back latches DQ X D X Q Q
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5 Reset Force output low when reset asserted Synchronous vs. asynchronous D Q Q reset D Q D reset Q D
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EEL6323-S11-HLec020-Sequencing-2spp - Lecture 20:...

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