EEL6323-S11-HLec021-Sequencing-2spp

EEL6323-S11-HLec021-Sequencing-2spp - Lecture 21:...

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1 Lecture 21: Sequential Circuits Setup and Hold time MS FF – Power PC Pulsed FF – HLFF, SDFF, SAFF Source: Ch 7 – J. Rabaey notes, Weste and Harris Notes Review: Timing Definitions T CQ : Propagation Delay from Ck to Q, assuming D has been set early enough relative to Ck T setup (U): minimum time between D change and the transparency Ck Edge, such that Q will be guaranteed to change T hold : minimum time D must be held after the triggering Clk edge T skew : spatial variation of clock arrival time between two points in the chip t CLK t D tc 2 q thold tsu t Q DATA STABLE DATA STABLE Register CLK DQ
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2 FF/Latch Design Balancing act Look for similarities in FF/Latch design Input stage output stage Internal Node D Q X Data Storage Internal Node – Stores sampled data. How? Static: stores as long as power is on Dynamic: store data in a capacitor (internal node capacitance)
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3 Sampling D How do you sample data? Sampling should occur for D=Hi and D=Lo
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This note was uploaded on 03/02/2012 for the course ESI 6323 taught by Professor Guan during the Spring '09 term at University of Florida.

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EEL6323-S11-HLec021-Sequencing-2spp - Lecture 21:...

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