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lec09-address-translation

lec09-address-translation - CS162 Operating Systems and...

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CS162 Operating Systems and Systems Programming Lecture 9 Address Translation February 15, 2012 Anthony D. Joseph and Ion Stoica http://inst.eecs.berkeley.edu/~cs162
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9.2 2/15/2012 Anthony D. Joseph and Ion Stoica CS162 ©UCB Spring 2012 Goals for Today Address Translation Schemes Segmentation Paging Multi-level translation Paged page tables Inverted page tables Note: Some slides and/or pictures in the following are adapted from slides ©2005 Silberschatz, Galvin, and Gagne. Many slides generated from lecture notes by Kubiatowicz.
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9.3 2/15/2012 Anthony D. Joseph and Ion Stoica CS162 ©UCB Spring 2012 Virtualizing Resources Physical Reality: Processes/Threads share the same hardware Need to multiplex CPU (CPU Scheduling) Need to multiplex use of Memory (Today) Why worry about memory multiplexing? The complete working state of a process and/or kernel is defined by its data in memory (and registers) Consequently, cannot just let different processes use the same memory Probably don’t want different processes to even have access to each other’s memory (protection)
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9.4 2/15/2012 Anthony D. Joseph and Ion Stoica CS162 ©UCB Spring 2012 Important Aspects of Memory Multiplexing Controlled overlap: Processes should not collide in physical memory Conversely, would like the ability to share memory when desired (for communication) Protection: Prevent access to private memory of other processes » Different pages of memory can be given special behavior (Read Only, Invisible to user programs, etc) » Kernel data protected from User programs Translation: Ability to translate accesses from one address space (virtual) to a different one (physical) When translation exists, process uses virtual addresses, physical memory uses physical addresses
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9.5 2/15/2012 Anthony D. Joseph and Ion Stoica CS162 ©UCB Spring 2012 Binding of Instructions and Data to Memory data1: dw 32 start: lw r1,0(data1) jal checkit loop: addi r1, r1, -1 bnz r1, loop checkit: … Process view of memory 0x 0300 00000020 0x0900 8C20 00C0 0x0904 0C00 0280 0x 0908 2021FFFF 0x090C 1420 0242 0x 0A00 Physical addresses Assume 4byte words 0x300 = 4 * 0x0C0 0x0C0 = 0000 1100 0000 0x300 = 0011 0000 0000
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9.6 2/15/2012 Anthony D. Joseph and Ion Stoica CS162 ©UCB Spring 2012 Binding of Instructions and Data to Memory 0x 0300 00000020 0x0900 8C20 00C0 0x0904 0C00 0280 0x 0908 2021FFFF 0x090C 1420 0242 0x 0A00 data1: dw 32 start: lw r1,0(data1) jal checkit loop: addi r1, r1, -1 bnz r1, loop checkit: … Process view of memory Physical addresses 8C2000C0 0C000340 2021FFFF 14200242 0x0900 0xFFFF 0x0300 0x0000 00000020 Physical Memory
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9.7 2/15/2012 Anthony D. Joseph and Ion Stoica CS162 ©UCB Spring 2012 Binding of Instructions and Data to Memory 0x300 00000020 0x900 8C2000C0 0x904 0C000280 0x908 2021FFFF 0x90C 14200242 0x0A00 data1: dw 32 start: lw r1,0(data1) jal checkit loop: addi r1, r1, -1 bnz r1, r0, loop checkit: … Process view of memory Physical addresses 0x0900 0xFFFF 0x0300 0x0000 Physical Memory ?
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