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Unformatted text preview: Page 1 CS162 Operating Systems and Systems Programming Lecture 11 Page Allocation and Replacement February 27, 2012 Anthony D. Joseph and Ion Stoica http://inst.eecs.berkeley.edu/~cs162 11.2 2/27/2012 Anthony D. Joseph and Ion Stoica CS162 UCB Spring 2012 Goals for Today Page Replacement Policies FIFO, LRU Clock Algorithm Working Set/Thrashing Note: Some slides and/or pictures in the following are adapted from slides 2005 Silberschatz, Galvin, and Gagne. Many slides generated from my lecture notes by Kubiatowicz. 11.3 2/27/2012 Anthony D. Joseph and Ion Stoica CS162 UCB Spring 2012 Memory Topics (61C and 162) Topic 61C 162 Protection HW-based address spaces HW-based address spaces, SW- based strong typing, SW fault isolation Virtual Memory Base & bound and single- level paging approaches Base & bound, swapping, multiple segments, paging, multi-level, inverted page table approaches. Shared memory and msg passing. Caching Mem hierarchy, temporal/ spatial locality, 3 sources of cache misses, direct/ associative caches, write- through/back policies, access time calc Mem hierarchy, temporal/spatial locality, ve sources of cache misses, direct/associative caches, write- through/back policies, access time calc, context switch implications TLB Basic concept Concept and overlapped with cache Paging Overview, LRU algorithm Detailed steps, analyzing algorithms, approximating LRU, implementing second-change and nth chance algorithms, working sets 11.4 2/27/2012 Anthony D. Joseph and Ion Stoica CS162 UCB Spring 2012 Review: Caching Applied to Address Translation Problem: address translation expensive (especially multi-level) Solution: cache address translation (TLB) Instruction accesses spend a lot of time on the same page (since accesses sequential) Stack accesses have denite locality of reference Data accesses have less page locality, but still some Data Read or Write (untranslated) CPU Physical Memory TLB Translate (MMU) No Virtual Address Physical Address Yes Cached? S a v e R e s u l t Page 2 11.5 2/27/2012 Anthony D. Joseph and Ion Stoica CS162 UCB Spring 2012 Here is how this might work with a 4K cache: What if cache size is increased to 8KB? Overlap not complete Need to do something else. See CS152/252 Another option: Virtual Caches Tags in cache are virtual addresses Translation only happens on cache misses TLB 4K Cache 10 2 00 4 bytes index 1 K page # disp 20 assoc lookup 32 Hit/ Miss PA Data Hit/ Miss = PA Overlapping TLB & Cache Access 11.6 2/27/2012 Anthony D. Joseph and Ion Stoica CS162 UCB Spring 2012 Review: Paging & Address Translation Physical Address: Offset Physical Page # Virtual Address: Offset Virtual P2 index Virtual P1 index PageTablePtr Page Table (1 st level) Page Table (2 nd level) Physical Memory: 11.7 2/27/2012 Anthony D. Joseph and Ion Stoica CS162 UCB Spring 2012 Page Table (2 nd level) PageTablePtr Page Table (1 st level) Review: Translation Look-aside Buffer...
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