final_2010 - ECE 553: Testing and Testable Design of...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2010-2011 Final Examination CLOSED BOOK Kewal K. Saluja Date: December 21, 2010 Place: Room 1153 Mechanical Engineering Time: 5:05 - 7:05 PM Duration: 120 minutes PROBLEM TOPIC POINTS SCORE 1 Test Economics 12 2 Testability Analysis 13 3 Test Generation 13 4 Memory Test 11 5 Pseudo-exhaustive test 10 6 DFT: Full and Partial scan 11 7 Partial scan 9 8 Boundary Scan 9 9 BIST 12 TOTAL 100 Last Name: First Name: Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Use extra sheets if you need more space to write 1 Fall 2010 (Lec: Saluja, TA: Ganju) ECE 553: Testing and Testable Design of Digital Systems 1. ( 12 points ) Test Economics A manufacturer of ICs uses the following yield equation for its product. Y ( T ) = [1 + Taf/β ]- β In this equation T is fault coverage, a is area of the chip, and f and β are process parameters. The values of the process parameters are as follows: f = 1.48 faults/ sq. cm. and β = 0.14 (a) ( 6 points ) For the area of chip to be 0.95 sq cm and fault coverage to be 94% determine the percent yield and defect level in parts per million (PPM) for this product. (b) ( 6 points ) The manufacturer is not too satisfied with this yield and defect level. It wishes to reduce the defect level to below 1000 PPM but realizes that such a drastic change in defect level will require DFT that will increase the chip area by 10%. The manufacturer will continue to use the the same process for its modified product. i. ( 2 points ) What will be the yield of the modified product if the manufacturer does not change the tests and test strategy? ii. ( 4 points ) Determine the fault coverage the manufacturer will need to meet its goal of reduced defect level. 2 Fall 2010 (Lec: Saluja, TA: Ganju) ECE 553: Testing and Testable Design of Digital Systems 2. ( 13 points ) Testability Analysis For a part of a large combinational circuit shown in Figure 1, compute the SCOAP controlla- bility and observability values for each line listed in the table below. Some of the values are provided and they are sufficient to deduce all the remaining values. Some of the values may in the table for your consistency check. A A1 A2 B C D E F F1 F2 G H I Figure 1: Testability analysis values Line # CC0 CC1 CO Line # CC0 CC1 CO A 30 A2 30 B F 70 74 C 25 30 F1 70 D 50 20 F2 70 E 12 35 37 G 51 46 50 H A1 30 I 3 Fall 2010 (Lec: Saluja, TA: Ganju) ECE 553: Testing and Testable Design of Digital Systems 3. ( 13 points ) Test Generation Consider the combinational circuit given below. A PODEM like test generator creates a decision tree shown below during the test generation process for the fault marked (line L stuck-at 0) in the circuit....
View Full Document

This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at University of Wisconsin.

Page1 / 15

final_2010 - ECE 553: Testing and Testable Design of...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online