final-2011

final-2011 - ECE 553: Testing and Testable Design of...

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Unformatted text preview: ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of WisconsinMadison ECE 553 : Testing and Testable Design of Digital Systems Fall 2011-2012 Final Examination CLOSED BOOK Kewal K. Saluja Date: December 17, 2011 Place: Room 2540 Engineering Hall Time: 2:45 - 4:45 PM Duration: 120 minutes PROBLEM TOPIC POINTS SCORE 1 Test Economics 15 2 Fault Simulation 10 3 Test Generation 6 4 Test Compaction 8 5 Memory Test 14 6 Pseudo-exhaustive test 10 7 DFT: Full and Partial scan 16 8 BIST 12 9 Boundary Scan 9 TOTAL 100 Last Name: First Name: Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Use extra sheets if you need more space to write 1 Fall 2011 (Lec: Saluja, TA: Millican) ECE 553: Testing and Testable Design of Digital Systems 1. ( 15 points ) Test Economics A board manufacturer uses 25 ICs of the same kind. The IC vendor provided the following specifications of its product: Area of the IC, A = 0.75 sq cm. Fault density, f = 1.45 faults/sq cm Clustering factor, = 0.11 Fault coverage, T = 90% Cost of the IC = $ 4.00 Now answer the following, and while answering you must show your work. (a) ( 3 points ) Determine the Defect Level of the product sold by the IC vendor. (b) ( 5 points ) Determine the average cost of producing a good board. You can ignore the cost of printed circuit, the board hardware, and the test equipment. 2 Fall 2011 (Lec: Saluja, TA: Millican) ECE 553: Testing and Testable Design of Digital Systems (c) ( 7 points ) The board manufacturer is willing to pay $0.50 more for each IC, provided the IC vendor will raise the fault coverage to 95%. Is this a good deal for the board manufacturer? You must provide a quantitative reasoning and you must show your work. 3 Fall 2011 (Lec: Saluja, TA: Millican) ECE 553: Testing and Testable Design of Digital Systems 2. ( 10 points ) Parallel Fault Simulation The circuit of Fig 1 is to be simulated using parallel fault simulation method for the following input pattern: A B C = 1 0 1 A B C 1 3 2 4 5 7 8 9 6 Figure 1: Combinational Circuit for Parallel Fault Simulation Assuming that the word size of a computer is 5 bits and the bits are numbered from 0 to 4 starting from the right most bit as shown in the Fig 2. bit 0 bit 4 Fault Free 7/5/1 6/1 4/1 3/1/1 Figure 2: Bits and Faults to be Injected You are to inject the faults shown in Fig 1 at the bit positions shown in Fig 2. Please pay attention to the correct bit position for each fault. If your choice of positions is different, you will not be given any credit. (a) ( 2 point ) Based on the information provided, marked the lines in the figure, for which the faults are to be simulated....
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This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at Wisconsin.

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final-2011 - ECE 553: Testing and Testable Design of...

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