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# hw1 - ECE 553 Testing and Testable Design of Digital...

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ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2011 Assignment #1 Date: Thursday, September 8, 2011 Due date: Thursday, September 22, 2011, in class 1. A certain fabrication process produces 80% good devices. The testing mechanism for the finished ICs has an accuracy of 96%. Find the yield and the defect-level of the ICs. Note: This problem is similar to Problem 1-1 of the text and does not use the yield model of chapter 3. 2. (Bushnell and Agrawal) Problem 1-4 Note: Use Example 1.2 in the textbook for ATE purchase price, deprecation rate, maintenance, and operating cost 3. (Bushnell and Agrawal) Problem 2-4 Note: Assume that the setup time is 400ps andt the clock-to-Q delay is 450ps. Draw waveform for input/output to explain your test method. 4. (Bushnell and Agrawal) Problem 3-6 but use the following values of f , β, T : f = 1 . 4 β = 0 . 13 T = 0 . 94 5. (Bushnell and Agrawal) Problem 3-7

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hw1 - ECE 553 Testing and Testable Design of Digital...

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