hw1 - ECE 553: Testing and Testable Design of Digital...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2011 Assignment #1 Date: Thursday, September 8, 2011 Due date: Thursday, September 22, 2011, in class 1. A certain fabrication process produces 80% good devices. The testing mechanism for the ±nished ICs has an accuracy of 96%. Find the yield and the defect-level of the ICs. Note: This problem is similar to Problem 1-1 of the text and does not use the yield model of chapter 3. 2. (Bushnell and Agrawal) Problem 1-4 Note: Use Example 1.2 in the textbook for ATE purchase price, deprecation rate, maintenance, and operating cost 3. (Bushnell and Agrawal) Problem 2-4 Note: Assume that the setup time is 400ps andt the clock-to-Q delay is 450ps. Draw waveform for input/output to explain your test method. 4. (Bushnell and Agrawal) Problem 3-6 but use the following values of
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at Wisconsin.

Page1 / 2

hw1 - ECE 553: Testing and Testable Design of Digital...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online