hw1_sol - ECE 553: Testing and Testable Design of Digital...

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Unformatted text preview: ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of WisconsinMadison ECE 553 : Testing and Testable Design of Digital Systems Fall 2011 Assignment #1 Date: Thursday, September 8, 2011 Due date: Thursday, September 22, 2011, in class SOLUTION 1. A certain fabrication process produces 80% good devices. The testing mechanism for the finished ICs has an accuracy of 96%. Find the yield and the defect-level of the ICs. Note: This problem is similar to Problem 1-1 of the text and does not use the yield model of chapter 3. Use the following convention for this problem: PQ: chip is good P: chip passes the test FQ: chip is bad F: chip fails the test A 80% good device production means, Prob ( PQ ) = 0 . 80 and Prob ( FQ ) = 0 . 20. Sim- ilarly, from the given data, we can see that Prob ( P/PQ ) = 0 . 96 and Prob ( P/FQ ) = . 04. We have to caluclate the probability of passing Prob ( P ) ie. the yield. Prob(P) = Prob(P / PQ) Prob(PQ) + Prob(P / FQ) Prob(FQ) = 0 . 96 . 80 + 0 . 04 . 20 = 0 . 776 Defect level = Bad chips that pass tests All chips that pass tests = Prob ( FQ | P ) = Prob ( P | FQ ) Prob ( FQ ) Prob ( P ) = . 04 . 20 . 776 = 0 . 010309 The defect level is 10 , 309 ppm (parts per million) and the yield is 77.6%. 1 Fall 2011 (Lec: Saluja, TA: Millican) ECE 553: Testing and Testable Design of Digital Systems 2. (Bushnell and Agrawal) Problem 1-4 Note: Use Example 1.2 in the textbook for ATE purchase price, deprecation rate, maintenance, and operating cost Following Example 1.2 of the book (pp. 10-11), we obtain ATE purchase price = $1 . 2 M + 256 $3 , 000 = $1 . 968 M Assuming a 20% per year linear rate of depreciation, a maintenance cost of 2% of the...
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hw1_sol - ECE 553: Testing and Testable Design of Digital...

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