hw2 - ECE 553: Testing and Testable Design of Digital...

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ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2011 Assignment #2 Date Tuesday, September 27, 2011 Due date Thursday, October 6, 2011 1. (10 points) For the logic circuit in ±gure 1, Compute a) the total number of single stuck-at faults b) the total number of stuck-open faults c) the total number of all possible multiple stuck-at fault combinations (assume 2-inputs NANDs and NORs use 4 Transistors, 2-input ANDs and OFs use 6 transistors, and NOTs use 2 transistors). Figure 1: Figure for Problem 1 2. (15 points) (Bushnell and Agrawal) Problem 4.5 3. (10 points) Show that the two faults a s-a-0 and c s-a-1 are equivalent in the circuit of ±gure 2. 1 Fall 2011 (Lec: Saluja, TA: Millican)
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ECE 553: Testing and Testable Design of Digital Systems Figure 2: Figure for Problem 3 4. (30 points) For this problem you will use the circuit given in Figure 3.
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This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at Wisconsin.

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hw2 - ECE 553: Testing and Testable Design of Digital...

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