hw4sol

# Hw4sol - ECE 553 Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison

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Unformatted text preview: ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2011 Assignment #4 Solution 1. (Bushnell and Agrawal) Problem 8.2 It requires just one vector to initialize the circuit. If the initial state is unknown, i.e., C n = X , the vector A n = B n = 1 initializes the state to 1, irrespective of the presence of any fault at the output S n . Given this state, detection of any output fault at the output reduces to a combinational ATPG problem of setting the output to the opposite value. This can be done by a single vector: ( A n = 0 ,B n = 0) will set the output to 1 or ( A n = 0 ,B n = 1) will set it to 0. Thus, just two vectors, an initialization vector 11 followed by an appropriate vector to set the output, will detect the output fault in the circuit of Figure 8.3 (see page 215 of the book.) 2. (Bushnell and Agrawal) Problem 8.4 The required test has two steps: (a) Fault activation. Assuming the present state to be unknown, we set the next state to 1. For C n = X , backward justification of C n +1 = 1 in Figure 8.3 (see page 215 of the book) gives us A n = 1 and B n = 1. (b) Path sensitization. For the next vector, the above next state becomes the present state and the fault C n s-a-0 is sensitized. We sensitize a path from C n to S n by setting A n = 1 and B n = 1....
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## This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at Wisconsin.

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Hw4sol - ECE 553 Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison

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