hw5 - ECE 553: Testing and Testable Design of Digital...

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ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2011 Assignment #5 Date : Thursday, November 10. 2011 Due Date : Tuesday, November 22, 2011 Turn in to TA by 3:00 PM 1. (Pseudo-combinational circuit) For this problem, you need to use a sequential circuit available in ~ece553/TESTCAD/nets/hw5-circuits/hw5_circuit_1 (a) Derive a combinational circuit by replacing each ±ip-±op (LATCH) to a bu²er (BUF). This is known as the pseudo-combinational transformation, which can be applied to any cycle-free clocked sequenctial circuit. (b) Derive a test for the circuit obtained after (a) for the fault “7 0 0” and “9 0 1”. (You can do this either by hand or by ’podem’ in the testcad toolset). (c) Verify that the fault “7 0 0” can be detected in the original sequential circuit by repeating the generated vector for three clock cycles. (d) At this point you found that “9 0 1” is redundant in the pseudo-combinational
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hw5 - ECE 553: Testing and Testable Design of Digital...

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