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# hw5sol - ECE 553 Testing and Testable Design of Digital...

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ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2011 Assignment #5 Solution 1. For this problem, you need to use a sequential circuit available in ~ece553/TESTCAD/nets/hw5-circuits/hw5_circuit_1 (a) Derive a combinational circuit by replacing each flip-flop (LATCH) to a buffer (BUF). This is known as the pseudo-combinational transformation, which can be applied to any cycle-free clocked sequenctial circuit. Answer: The circuit is obtained by replacing flip-flop (LATCH) to a buffer (BUF) as follows: 1 PI 3 7 ; 2 PI 4 ; 3 OR 5 ; 4 BUF 3 6 9 ; 5 BUF 6 ; 6 NAND 8 10 11 ; 7 NOT 10 ; 8 BUF 10 ; 9 BUF 11 ; 10 OR 12 ; 11 OR 13 ; 12 PO ; 13 PO ; (b) Derive a test for the circuit obtained after (a) for the fault “7 0 0” and “9 0 1”. (You can do this either by hand or by PODEM in the testcad toolset). For the fault 7 0 0 : Input = 1/0 2/1. For the fault 9 0 1 : Test does not exist. 1 Fall 2011 (Lec: Saluja, TA: Millican)

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ECE 553: Testing and Testable Design of Digital Systems (c) Verify that the fault “7 0 0” can be detected in the original sequential circuit by repeating the generated vector for three clock cycles. A B Z C D E F1 F2 F3 Z C D E s-a-0 A B 1 1/0 0 1 1 0 1 1/0 s-a-0 1,1,1,1 0,0,0,0 X,1,1,1 X,X,1,1 X,1,1,1 X,X,0,0 X,X,X,0 1/0,1/0,1/0,1/0 1/X,1/X,1/X,1/0 Pseudo-combinational circuit for the sequential circuit of Figure 8.9.. Test simulation in sequential circuit. (d) At this point you found that “9 0 1” is redundant in the pseudo-combinational circuit. Now, try to use the sequential test generator (fastest in testcad toolset) on the original circuit to generate a test vectors for “9 0 1”. Verify if the generated test sequence indeed detects the fault by hand simulation. You’ll find “9 0 1” is not redundant in the original circuit.
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