Lecture_1 - 9/1/2011 Overview Motivation About the Course...

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9/1/2011 1 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Motivation and Introduction 9/1/2011 2 Overview Motivation About the Course and the Instructor – Conduct – Outline – Coursepack Introduction – VLSI realization process – Contract between design house and fab vendor – Test v/s verification – Need for testing: doing business, ideal v/s real testing – Levels of testing – rule of 10 (or 20) – Cost of manufacturing 9/1/2011 3 Motivation • Where do the manufacturing $ go? • Overhead of one or two photomicrographs – What is test on a chip? • Course conduct – Your responsibilities and mine • Course outline • Course material information – References and reading material 9/1/2011 4 Motivation: Moore’s Law Complexity Growth of VLSI circuits Source (Copp, Int. AOC EW Conf., 2002 ) 9/1/2011 5 Thermal Effect of Moore’s law Moore’s law Greater packaging densities Higher power densities Higher temperature Effects Reliability Performance Power Cooling cost Introduction: Challenges under deep submicron technologies (Yao) Chip size decreases Power density increases Leakage power make it worse Chip becomes hotter Source: Intel Source: Intel Source: Wang et al. ISPD2003
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9/1/2011 2 9/1/2011 7 Microprocessor Cost per Transistor Cost of testing will EXCEED cost of design/manufacturing ( Source: ITR-Semiconductor, 2002) 9/1/2011 8 VLSI Realization Process Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development Technology Directions: SIA Roadmap Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 90 45 32 22 Mtrans/cm
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This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at Wisconsin.

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Lecture_1 - 9/1/2011 Overview Motivation About the Course...

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