Lecture_3 - 9/2/2011 4 Test Coverage from Fault Simulator...

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9/2/2011 1 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Test Economics: Cost analysis and model fitting 9/2/2011 2 Benefits and Costs of DFT Design and test + / - + / - + / - Fabri- cation + + + Manuf. Test - - - Level Chips Boards System Maintenance test - Diagnosis and repair - - Service interruption - + Cost increase - Cost saving +/- Cost increase may balance cost reduction 9/2/2011 3 VLSI Defects Wafer Defects Faulty chips Good chips Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77
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Unformatted text preview: 9/2/2011 4 Test Coverage from Fault Simulator Stuck-at fault coverage Vector number 9/2/2011 5 Measured Chip Fallout Vector number Measured chip fallout 9/2/2011 6 Model Fitting Y ( T ) for Af = 2.1 and b = 0.083 Measured chip fallout (1) = 0.7623 Chip fallout and computed 1-( ) Stuck-at fault coverage, Chip fallout vs. fault coverage 9/2/2011 2 9/2/2011 7 Computed DL Stuck-at fault coverage (%) Defect level in ppm 237,700 ppm ( Y = 76.23%)...
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This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at Wisconsin.

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Lecture_3 - 9/2/2011 4 Test Coverage from Fault Simulator...

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