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Unformatted text preview: 9/20/2011 1 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Fault Simulation 9/20/2011 2 Overview Problem and motivation Fault simulation algorithms Serial Parallel Deductive Concurrent Other algorithms Random Fault Sampling Summary 9/20/2011 3 Problem and Motivation Fault simulation Problem: Given A circuit A sequence of test vectors A fault model Determine Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults Motivation Determine test quality and in turn product quality Find undetected fault targets to improve tests 9/20/2011 4 Usages of Fault Simulators Test grading as explained before Test Generation Fault diagnosis Design for test (DFT) identification of points that may help improve test quality Fault-tolerance identification of damage a fault can cause 9/20/2011 5 Alternatives and Their Limitations Prototyping with fault injection capabilities Costly Limited fault injection capability Design changes hard to implement Long lead time Hardware emulators Costly Require special hardware 9/20/2011 6 Fault Simulator in a VLSI Design Process Verified design netlist Verification input stimuli Fault simulator Test vectors Modeled fault list Test generator Test compactor Fault coverage ? Remove tested faults Delete vectors Add vectors Low Adequate Stop 9/20/2011 2 9/20/2011 7 Fault Simulation Scenario Circuit model: mixed-level Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals High-level models (memory, etc.) with pin faults Signal states: logic Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits Four states (0, 1, X, Z) for sequential MOS circuits Timing: Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback 9/20/2011 8 Fault Simulation Scenario (continued) Faults: Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use...
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- Winter '08