Lecture_11

Lecture_11 - Overview ECE 553 TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Motivation Sequential circuit ATPG An example test generation

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10/11/2011 1 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Sequential circuit ATPG 10/11/2011 2 Overview Motivation Sequential circuit ATPG An example test generation Time-frame expansion • Nine-valued logic • ATPG implementation and drivability • Complexity of ATPG • Cycle-free and cyclic circuits Test generations systems – Classification – Forward time test generator – FASTEST – General comments – Simulation based test generators – contest, strategate Summary 10/11/2011 3 Motivation • A sequential circuit has memory in addition to combinational logic. • Test for a fault in a sequential circuit is a sequence of vectors, which • Initializes the circuit to a known state • Activates the fault, and • Propagates the fault effect to a primary output 10/11/2011 4 Sequential circuit ATPG • Methods – Time-frame expansion methods • Forward time, reverse time, forward and reverse time – Simulation-based methods 10/11/2011 5 Example: A Serial Adder FF A n B n C n n+1 S n s-a-0 1 1 1 1 1 X D Combinational logic 10/11/2011 6 Time-Frame Expansion n n n n+1 1 n s-a-0 1 1 1 1 Combinational logic n-1 s-a-0 1 1 1 1 Combinational logic n-1 1 1 n-1 n-1 Time-frame -1 0
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10/11/2011 2 10/11/2011 7 Concept of Time-Frames • If the test sequence for a single stuck-at fault contains n vectors, • Replicate combinational logic block n times • Place fault in each block • Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Comb. block Fault Time- frame 0 Time- frame -1 Time- frame - n +1 Unknown or given Init. state Vector 0 Vector -1 Vector - +1 PO 0 PO -1 PO - +1 State variables Next state 10/11/2011 8 Example for Logic Systems FF2 FF1 A B s-a-1 10/11/2011 9 Five-Valued Logic (Roth) 0,1, D , D , X A B X 0 s-a-1 D 0 s-a-1 FF1 FF1 FF2 FF2 Time-frame -1 Time-frame 0 10/11/2011 10 Nine-Valued Logic (Muth) 0,1, 1/0, 0/1, 1/ X, 0/ X , X/ 0, X/ 1, X 0 s-a-1 0/1 0/ 0/ 0/1 X s-a-1 X /1 FF1 FF1 FF2 FF2 0/1 /1 Time-frame -1 Time-frame 0 10/11/2011 11 An implementation of ATPG • Select a PO for fault detection based on drivability analysis. • Place a logic value, 1/0 or 0/1 , depending on fault type and number of inversions. • Justify the output value from PIs, considering all necessary paths and adding backward time-frames. • If justification is impossible, then select another PO and repeat justification. • If the procedure fails for all reachable POs, then the fault is untestable. • If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the the fault is potentially detectable. 10/11/2011
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This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at Wisconsin.

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Lecture_11 - Overview ECE 553 TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Motivation Sequential circuit ATPG An example test generation

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