Lecture_12

# Lecture_12 - Overview ECE 553 TESTING AND TESTABLE DESIGN...

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10/18/2011 1 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Sequential circuit testing - Checking experiment approach 10/18/2011 2 Overview • Motivation and introduction • Model and fault model • Theory • Checking experiment design • Limitations of the method • Summary 10/18/2011 3 Motivation and Introduction • Ref: F.C. Hennie “Fault detection experiments for sequential circuits”, 5 th annual symposium on switching and automata theory, 1964. • Motivation – Test generation at higher level of abstraction in which only the function of the circuit is known but the implementation (structure) is not known 10/18/2011 4 An example • Consider testing a 4-bit ALU – We need not know the structure – we can determine the number of inputs and outputs. If the number is small we can test the circuit exhaustively. – Can such a technique be used for sequential circuits, even if it is fairly small, such as a small finite state machine. Such FSMs exist often in practice (embedded controllers are good examples of such FSMs). • Derivation of tests for such circuits is of interest for the following two reasons – Need not worry about the realization and underlying technology – Such tests can also be used for validation and verification 10/18/2011 5 Sequential circuit model • Two ways to express a state machine – State table – State diagram – M = (Q, I, O, NS, OU) Q = set of states I = set of inputs from an input alphabet O = set of outputs from an output alphabet NS = next state function OU = output function 10/18/2011 6 Fault model • Two formulations of the test problem – Given the behavior of the circuit (such as state table),

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## This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at University of Wisconsin.

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Lecture_12 - Overview ECE 553 TESTING AND TESTABLE DESIGN...

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