Lecture_15

Lecture_15 - 11/11/2011 Overview History and motivation...

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11/11/2011 1 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS I DDQ Current Testing 11/11/2011 2 Overview History and motivation Basic principle Faults detected by I DDQ tests Instrumentation difficulties Sematech study Limitations of I DDQ testing Summary 11/11/2011 3 Motivation • Early 1990’s – Fabrication Line had 50 to 1000 defects per million (dpm) chips IBM wants to get 3.4 defects per million (dpm) chips (0 defects, 6 s ) • Conventional way to reduce defects: Increasing test fault coverage Increasing burn-in coverage Increase Electro-Static Damage awareness • Newer way to reduce defects: I DDQ Testing – also useful for Failure Effect Analysis 11/11/2011 4 Basic Principle of I DDQ Testing – Measure I DDQ current through V ss bus 11/11/2011 5 Faults Detected by I DDQ Tests 11/11/2011 6 Stuck-at Faults Detected by I DDQ Tests Bridging faults with stuck-at fault behavior Levi – Bridging of a logic node to V DD or V SS few of these Transistor gate oxide short of 1 K W to 5 K W • Floating MOSFET gate defects – do not fully turn off transistor
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11/11/2011 2 11/11/2011 7 NAND Open Circuit Defect – Floating gate The fault manifests as stuck-at, weak ON for N-FET, or delay fault some manifestations can be tested by I DDQ tests 11/11/2011 8 Floating Gate Defects
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This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at Wisconsin.

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Lecture_15 - 11/11/2011 Overview History and motivation...

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