Lecture_16

Lecture_16 - 11/11/2011 Overview Definition Ad-hoc methods...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
11/11/2011 1 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS Design for Testability (DFT) - 1 11/11/2011 2 Overview • Definition • Ad-hoc methods Scan design – Design rules – Scan register – Scan flip-flops – Scan test sequences – Overhead – Scan design system • Summary 11/11/2011 3 Definition Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. • DFT methods for digital circuits: – Ad-hoc methods – Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan 11/11/2011 4 Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: Don’t-s and Do-s • Avoid asynchronous (unclocked) feedback. • Avoid delay dependant logic. • Avoid parallel drivers. • Avoid monostables and self-resetting logic. • Avoid gated clocks. • Avoid redundant gates. • Avoid high fanin fanout combinations. 11/11/2011 5 Ad-Hoc DFT Methods • Good design practices learnt through experience are used as guidelines: – Don’t-s and Do-s (contd.) • Make flip-flops initializable. • Separate digital and analog circuits. • Provide test control for difficult-to-control signals. • Buses can be useful and make life easier. • Limit gate fanin and fanout. • Consider ATE requirements (tristates, etc.) 11/11/2011 6 Ad-Hoc DFT Methods • Design reviews – Manual analysis • Conducted by experts. – Programmed analysis • Using design auditing tools – Programmed enforcement • Must use certain design practices and cell types. • Objective: Adherence to design guidelines and testability improvement techniques.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
11/11/2011 2 11/11/2011 7 Ad-Hoc DFT Methods • Disadvantages of ad-hoc DFT methods: • Experts and tools not always available. • Test generation is often manual with no guarantee of high fault coverage. • Design iterations may be necessary. 11/11/2011 8 Scan Design – Objectives • Simple read/write access to all or subset of storage elements in a design.
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at Wisconsin.

Page1 / 5

Lecture_16 - 11/11/2011 Overview Definition Ad-hoc methods...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online