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Unformatted text preview: 11/29/2011 1 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS Built-In Self-Test (BIST) - 1 11/29/2011 2 Overview: TPG and RC Motivation and economics Definitions Built-in self-testing (BIST) process BIST pattern generation (PG) BIST response compaction (RC) Aliasing definition and example Summary 11/29/2011 3 BIST Motivation Useful for field test and diagnosis (less expensive than a local automatic test equipment) Software tests for field test and diagnosis: Low hardware fault coverage Low diagnostic resolution Slow to operate Hardware BIST benefits: Lower system test effort Improved system maintenance and repair Improved component repair Better diagnosis at component level 11/29/2011 4 Costly Test Problems Alleviated by BIST Increasing chip logic-to-pin ratio harder observability Increasingly dense devices and faster clocks Increasing test generation and application times Increasing size of test vectors stored in ATE Expensive ATE needed for GHz clocking chips Hard testability insertion designers unfamiliar with gate- level logic, since they design at behavioral level In-circuit testing no longer technically feasible Circuit testing cannot be easily partitioned 11/29/2011 5 Design and test + / - + / - + / - Fabri- cation + + + Manuf. Test - - - Level Chips Boards System Maintenance test - Diagnosis and repair - - Service interruption - + Cost increase - Cost saving +/- Cost increase may balance cost reduction Benefits and Costs of BIST with DFT 11/29/2011 6 Economics BIST Costs Chip area overhead for: Test controller Hardware pattern generator Hardware response compacter Testing of BIST hardware Pin overhead -- At least 1 pin needed to activate BIST operation Performance overhead extra path delays due to BIST Yield loss due to increased chip area or more chips In system because of BIST Reliability reduction due to increased area Increased BIST hardware complexity happens when BIST hardware is made testable 11/29/2011 2 11/29/2011 7 BIST Benefits Faults tested: Single combinational / sequential stuck-at faults Delay faults Single stuck-at faults in BIST hardware BIST benefits Reduced testing and maintenance cost Lower test generation cost Reduced storage / maintenance of test patterns Simpler and less expensive ATE Can test many units in parallel Shorter test application times Can test at functional system speed 11/29/2011 8 Definitions BILBO Built-in logic block observer , extra hardware added to flip-flops so they can be reconfigured as an LFSR pattern generator or response compacter, a scan chain, or as flip-flops Concurrent testing Testing process that detects faults during normal system operation CUT Circuit-under-test Exhaustive testing Apply all possible 2 n patterns to a circuit with n inputs...
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