Lecture_20 - Overview Boundary Scan ECE 553 TESTING AND...

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12/9/2011 1 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS Boundary Scan 12/9/2011 2 Overview: Boundary Scan • Motivation • Bed-of-nails tester • System view of boundary scan hardware • Elementary scan cell Test Access Port (TAP) controller Boundary scan instructions • Summary 12/9/2011 3 Motivation for Standard Bed-of-nails printed circuit board tester gone We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance Nails would hit components Reduced spacing between PCB wires Nails would short the wires PCB Tester must be replaced with built-in test delivery system -- JTAG does that Need standard System Test Port and Bus Integrate components from different vendors Test bus identical for various components One chip has test hardware for other chips 12/9/2011 4 Bed-of-Nails Tester Concept 12/9/2011 5 Bed-of-Nails Tester 12/9/2011 6 Purpose of Standard Lets test instructions and test data be serially fed into a component-under-test (CUT) Allows reading out of test results Allows RUNBIST command as an instruction Too many shifts to shift in external tests JTAG can operate at chip, PCB, & system levels Allows control of tri-state signals during testing Lets other chips collect responses from CUT Lets system interconnect be tested separately from components Lets components be tested separately from wires
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12/9/2011 2 12/9/2011 7 System Test Logic 12/9/2011
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This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at University of Wisconsin.

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Lecture_20 - Overview Boundary Scan ECE 553 TESTING AND...

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