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midterm-2010 - ECE 553 Testing and Testable Design of...

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ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2010-2011 Midterm Examination CLOSED BOOK Kewal K. Saluja Date: November 11, 2010 Place: Room 1164 Mechanical Engineering (Class location) Time: 7:15 - 8:30 PM Duration: 75 minutes PROBLEM TOPIC POINTS SCORE 1 General Questions 10 2 Test Economics 12 3 Modeling 13 4 Fault Modeling 12 5 Fault Simulation 12 6 SCOAP Computation 10 7 Test Generation - Comb 12 8 Test Generation - Seq 10 9 Checking Seq 9 TOTAL 100 Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Last Name (Please print): First Name: ID Number: 1 Fall 2010 (Lec: Saluja, TA: Ganju)
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ECE 553: Testing and Testable Design of Digital Systems 1. ( 10 points ) General Questions Answer the following in brief and to the point. (a) ( 1 points ) What defect model is used to derive the yield equation in the paper by William and Brown included in the reading material? (b) ( 1 points ) Name one forward time sequential test generator. (c) ( 1 points ) Name one reverse time sequential test generator. (d) ( 1 points ) Name one simulation based sequential test generator. (e) ( 2 points ) Should redundancy always be removed from a circuit? Explain. (f) ( 2 points ) Name two techniques that can be used to reduce the number of test patterns for a combinational circuit while still providing the same or better fault coverage. (g) ( 1 points ) Is the claim that concurrent fault simulator in general requires larger memory than deductive fault simulator, true? (h) ( 1 points ) Is it possible for a circuit to have a Distinguishing sequence but not have a synchronizing sequence? 3 Fall 2010 (Lec: Saluja, TA: Ganju)
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ECE 553: Testing and Testable Design of Digital Systems 2. ( 12 points ) Test Economics While answering the following you must show your work. A Manufacturer of an IC performs two types of tests on its product. (a) ( 6 points ) The type 1 test is for defect testing to sort out defective devices from the good devices. Based on its fabrication line and experience, the manufacturer has found that 96% fault coverage is sufficient for the IC manufactured by it. The area of the IC is 0.60 sq. cm., the fault density is 1.5 faults/sq. cm., and the fault clustering factor β is 0.15. i. ( 3 points ) What is the Yield of the type 1 test that performs defect testing ? ii. ( 3 points ) What is the defect level in the devices that pass type 1 test performed for defect testing ? (b) ( 4 points ) The type 2 test is performed only on the ICs which pass the type 1 test, i.e. are expected to be defect free. This test is for speed binning . The objective here is to divide all the ICs into two bins, fast bin and slow bin . Devices which are in the fast bin can run at 1.5 GHz or more (faster ICs) and are sold at higher price relative to the devices which are in slow bin (slower ICs). The following information is given about this testing stage.
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