midterm-2010

midterm-2010 - ECE 553: Testing and Testable Design of...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2010-2011 Midterm Examination CLOSED BOOK Kewal K. Saluja Date: November 11, 2010 Place: Room 1164 Mechanical Engineering (Class location) Time: 7:15 - 8:30 PM Duration: 75 minutes PROBLEM TOPIC POINTS SCORE 1 General Questions 10 2 Test Economics 12 3 Modeling 13 4 Fault Modeling 12 5 Fault Simulation 12 6 SCOAP Computation 10 7 Test Generation - Comb 12 8 Test Generation - Seq 10 9 Checking Seq 9 TOTAL 100 Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Last Name (Please print): First Name: ID Number: 1 Fall 2010 (Lec: Saluja, TA: Ganju)
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ECE 553: Testing and Testable Design of Digital Systems This page is left blank intentionally 2 Fall 2010 (Lec: Saluja, TA: Ganju)
Background image of page 2
ECE 553: Testing and Testable Design of Digital Systems 1. ( 10 points ) General Questions Answer the following in brief and to the point. (a) ( 1 points ) What defect model is used to derive the yield equation in the paper by William and Brown included in the reading material? (b) ( 1 points ) Name one forward time sequential test generator. (c) ( 1 points ) Name one reverse time sequential test generator. (d) ( 1 points ) Name one simulation based sequential test generator. (e) ( 2 points ) Should redundancy always be removed from a circuit? Explain. (f) ( 2 points ) Name two techniques that can be used to reduce the number of test patterns for a combinational circuit while still providing the same or better fault coverage. (g) ( 1 points ) Is the claim that concurrent fault simulator in general requires larger memory than deductive fault simulator, true? (h) ( 1 points ) Is it possible for a circuit to have a Distinguishing sequence but not have a synchronizing sequence? 3 Fall 2010 (Lec: Saluja, TA: Ganju)
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ECE 553: Testing and Testable Design of Digital Systems 2. ( 12 points ) Test Economics While answering the following you must show your work. A Manufacturer of an IC performs two types of tests on its product. (a) ( 6 points ) The type 1 test is for defect testing to sort out defective devices from the good devices. Based on its fabrication line and experience, the manufacturer has found that 96% fault coverage is suFcient for the IC manufactured by it. The area of the IC is 0.60 sq. cm., the fault density is 1.5 faults/sq. cm., and the fault clustering factor β is 0.15. i. ( 3 points ) What is the Yield of the type 1 test that performs defect testing ? ii. ( 3 points ) What is the defect level in the devices that pass type 1 test performed for defect testing ? (b) (
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/13/2012 for the course ECE 553 taught by Professor Ece553 during the Winter '08 term at Wisconsin.

Page1 / 19

midterm-2010 - ECE 553: Testing and Testable Design of...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online