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midterm-2010_solution

# midterm-2010_solution - ECE 553 Testing and Testable Design...

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Unformatted text preview: ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsinâ€“Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2010-2011 Midterm Examination SOLUTION CLOSED BOOK Kewal K. Saluja Date: November 11, 2010 Place: Room 1164 Mechanical Engineering (Class location) Time: 7:15 - 8:30 PM Duration: 75 minutes PROBLEM TOPIC POINTS SCORE 1 General Questions 10 2 Test Economics 12 3 Modeling 13 4 Fault Modeling 12 5 Fault Simulation 12 6 SCOAP Computation 10 7 Test Generation - Comb 12 8 Test Generation - Seq 10 9 Checking Seq 9 TOTAL 100 Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Last Name (Please print): SOLUTION First Name: ID Number: 1 Fall 2010 (Lec: Saluja, TA: Ganju) ECE 553: Testing and Testable Design of Digital Systems This page is left blank intentionally 2 Fall 2010 (Lec: Saluja, TA: Ganju) ECE 553: Testing and Testable Design of Digital Systems 1. ( 10 points ) General Questions Answer the following in brief and to the point. (a) ( 1 points ) What defect model is used to derive the yield equation in the paper by William and Brown included in the reading material? Random defects (b) ( 1 points ) Name one forward time sequential test generator. Fastest (c) ( 1 points ) Name one reverse time sequential test generator. There are many - HITEST is an example discussed in the paper (d) ( 1 points ) Name one simulation based sequential test generator. CONTEST - one of the example mentioned in the paper (e) ( 2 points ) Should redundancy always be removed from a circuit? Explain. From design point of view it may be desirable in some cases as in fault tolerant designs. (f) ( 2 points ) Name two techniques that can be used to reduce the number of test patterns for a combinational circuit while still providing the same or better fault coverage. Fault list reduction: fault equivalence, fault dominance, ... Compation: Static compaction, Dynamic compaction, reserve order simulation .. (g) ( 1 points ) Is the claim that concurrent fault simulator in general require larger memory that deductive fault simulator, true? Yes. The fault lists associated with a gate in deductive fault simulation are subset of the lists associated in concurrent fault simulation. (h) ( 1 points ) Is it possible for a circuit to have a Distinguishing sequence but not have a synchronizing sequence? Yes. A simple example is a modulo k counter without reset. 3 Fall 2010 (Lec: Saluja, TA: Ganju) ECE 553: Testing and Testable Design of Digital Systems 2. ( 12 points ) Test Economics While answering the following you must show your work. A Manufacturer of an IC performs two types of tests on its product....
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midterm-2010_solution - ECE 553 Testing and Testable Design...

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