midterm-2011

midterm-2011 - ECE 553 Testing and Testable Design of...

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ECE 553: Testing and Testable Design of Digital Systems 0.4pt0.4pt 0pt0.4pt Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2011-2012 Midterm Examination CLOSED BOOK Kewal K. Saluja Date: November 10, 2011 Place: Room 1153 Mechanical Engineering Time: 7:15 - 8:45 PM Duration: 100 minutes PROBLEM TOPIC POINTS SCORE 1 General Questions 10 2 Test Economics 15 3 Logic and Fault Modeling 14 4 Fault Simulation 13 5 SCOAP Computation 10 6 Test Generation - Comb. 16 7 Test Generation - Seq. 10 8 Checking Sequence 12 TOTAL 100 Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Last Name (Please print): First Name: ID Number: 1 Fall 2011 (Lec: Saluja, TA: Millican)

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ECE 553: Testing and Testable Design of Digital Systems 1. ( 10 points ) General Questions Answer the following in brief and to the point. (a) ( 1 points ) Give one reason as to why a circuit that is tested good may fail when a customer uses it. (b) ( 1 points ) What defect model is used to derive the yield equation in the paper by William and Brown included in the reading material? (c) ( 1 points ) If a fault f 1 is equivalent to f 2 and the fault f 1 dominates a fault f 3 , then which of these fault or faults can be deleted to reduce the the fault list for the purpose of fault detection. Give reason. (d) ( 2 points ) A single output combinational circuit is simulated using 3-value logic with some inputs speciFed (0s and 1s) while other inputs not speciFed (Xs). The output of the circuit is found to be a constant (0 or 1). Prove by proper reasoning or by an example that for the same input values and in the presence of a stuck-at fault in the circuit the output can be X. Use only the space provided. (e) ( 1 points ) A test algorithm which is capable of Fnding all tests for a fault in a combinational circuit can determine if a given fault in the circuit is redundant. Answer True or ±alse. 2 ±all 2011 (Lec: Saluja, TA: Millican)
ECE 553: Testing and Testable Design of Digital Systems (f) ( 1 points ) If the SCOAP CC0 value of a line in a circuit is 23, then using appropriate input assignment we can always set this line to logic 0. Answer True to False. (g) ( 1 points ) Circuits which have high fault coverage using Random Patterns are called Random Pattern . .............................. Circuits. (h) ( 1 points ) De±ne fault eFciency . (i) ( 1 points ) Is it possible for a circuit to have a Synchronizing Sequence but not have a Homing Sequence? Explain your answer. 3 Fall 2011 (Lec: Saluja, TA: Millican)

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ECE 553: Testing and Testable Design of Digital Systems 2. ( 15 points ) Test Economics Product details and process parameters of an IC being designed and fabricated by a Manufacturer are as follow: Area of the IC = 0.75 sq cm.
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midterm-2011 - ECE 553 Testing and Testable Design of...

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