midterm-2011_solution

midterm-2011_solution - ECE 553 Testing and Testable Design...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ECE 553: Testing and Testable Design of Digital Systems 0.4pt0.4pt 0pt0.4pt Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2011-2012 Midterm Examination CLOSED BOOK Kewal K. Saluja Date: November 10, 2011 Place: Room 1153 Mechanical Engineering Time: 7:15 - 8:55 PM Duration: 100 minutes PROBLEM TOPIC POINTS SCORE 1 General Questions 10 2 Test Economics 15 3 Logic and Fault Modeling 14 4 Fault Simulation 13 5 SCOAP Computation 10 6 Test Generation - Comb. 16 7 Test Generation - Seq. 10 8 Checking Sequence 12 TOTAL 100 Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Last Name (Please print): SOLUTION First Name: ID Number: 1 Fall 2011 (Lec: Saluja, TA: Millican) ECE 553: Testing and Testable Design of Digital Systems 1. ( 10 points ) General Questions Answer the following in brief and to the point. (a) ( 1 points ) Give one reason as to why a circuit that is tested good may fail when a customer uses it. Less than 100% fault coverage Presence of faults not modeled by the fault model ... (b) ( 1 points ) What defect model is used to derive the yield equation in the paper by William and Brown included in the reading material? Random defects (c) ( 1 points ) If a fault f 1 is equivalent to f 2 and the fault f 1 dominates a fault f 3 , then which of these fault or faults can be deleted to reduce the the fault list for the purpose of fault detection. Give reason. Only f 3 needs to be kept. Fault f 1 is equivalent to f 2 , therefor we can remove either one of them. In particular we can delete f 2 . Next f 1 dominates f 3 , therefore we can delete f 1 . (d) ( 2 points ) A single output combinational circuit is simulated using 3-value logic with some inputs specified (0s and 1s) while other inputs not specified (Xs). The output of the circuit is found to be a constant (0 or 1). Prove by proper reasoning or by an example that for the same input values and in the presence of a stuck-at fault in the circuit the output can be X. Use only the space provided. A simple example will be to consider a NAND with two inputs A and B. For A =0 and B = X, the output will be 1. Now in the presence of a fault A s-at-1 the faulty gate will produce and output X. (e) ( 1 points ) A test algorithm which is capable of finding all tests for a fault in a combinational circuit can determine if a given fault in the circuit is redundant. Answer True or False. True 2 Fall 2011 (Lec: Saluja, TA: Millican) ECE 553: Testing and Testable Design of Digital Systems (f) ( 1 points ) If the SCOAP CC0 value of a line in a circuit is 23, then using ap- propriate input assignment we can always set this line to logic 0. Answer True to False....
View Full Document

Page1 / 19

midterm-2011_solution - ECE 553 Testing and Testable Design...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online