wk3 Lec

wk3 Lec - CSE140: Components and Design Techniques for...

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Sources: TSR, Katz, Boriello & Vahid 1 CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing
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Sources: TSR, Katz, Boriello & Vahid 2 Where we are now… What we covered thus far: – Number representations – Boolean algebra – Logic representations (e.g. SOP and POS) – K-maps – Algorithm for simplification HW#2 due; HW#3 assigned Where we are going: – Mux/Demux – Adders – Multiplier – Hazards – Multilevel logic – Regular logic – ALUs
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Sources: TSR, Katz, Boriello & Vahid 3 CSE140: Components and Design Techniques for Digital Systems Muxes and demuxes Tajana Simunic Rosing
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Sources: TSR, Katz, Boriello & Vahid 4 Pass transistor – Mux building block Connects X & Y when A=1, else X & Y disconnected A_b = not(A) Fig source: Prof. Subhashish Mitra
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Sources: TSR, Katz, Boriello & Vahid 5 Mux Internal Design • Selects input to connect to Y selA == 1: connects A to Y selB == 1: connects B to Y Fig source: Prof. Subhashish Mitra 2 × 1 i1 i0 s0 1 d 2 × 1 i1 i0 s0 0 d 2 × 1 i1 i0 s0 d 2x1 mux A B Y Y A B A B
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Sources: TSR, Katz, Boriello & Vahid 6 2 -1 I0 I1 I2 I3 I4 I5 I6 I7 A B C 8:1 mux Z I0 I1 I2 I3 A B 4:1 mux Z I0 I1 A 2:1 mux Z k=0 n Multiplexers 2:1 mux: Z = A'I 0 + AI 1 4:1 mux: Z = A'B'I 0 + A'BI 1 + AB'I 2 + ABI 3 8:1 mux: Z = A'B'C'I 0 + A'B'CI 1 + A'BC'I 2 + A'BCI 3 + AB'C'I 4 + AB'CI 5 + ABC'I 6 + ABCI 7 In general: Z = (m k I k ) – in minterm shorthand form for a 2 n :1 Mux
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Sources: TSR, Katz, Boriello & Vahid 7 N-bit Mux Example Four possible display items Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles remaining (M) -- each is 8-bits wide Choose which to display using two inputs x and y Use 8-bit 4x1 mux
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Sources: TSR, Katz, Boriello & Vahid 8 C0 C1 C2 Function Comments 0 0 0 1 always 1 0 0 1 A + B logical OR 0 1 0 (A • B)' logical NAND 0 1 1 A xor B logical xor 1 0 0 A xnor B logical xnor 1 0 1 A • B logical AND 1 1 0 (A + B)' logical NOR 1 1 1 0 always 0 Mux example: Logical function unit C2 C0 C1 0 1 2 3 4 5 6 7 S2 8:1 MUX S1 S0 F
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Sources: TSR, Katz, Boriello & Vahid 9 Multiplexers as general-purpose logic A 2 n-1 :1 multiplexer can implement any function of n variables with n-1 variables used as control inputs and the data inputs tied to the last variable or its complement Example: F(A,B,C) = AC + BC ' + A ' B ' D
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Sources: TSR, Katz, Boriello & Vahid 10 1:2 Decoder: O0 = G S’ O1 = G S 2:4 Decoder: O0 = G S1’ S0’ O1 = G S1’ S0 O2 = G S1 S0’ O3 = G S1 S0 3:8 Decoder: O0 = G S2’ S1’ S0’ O1 = G S2’ S1’ S0 O2 = G S2’ S1 S0’ O3 = G S2’ S1 S0 O4 = G S2 S1’ S0’ O5 = G S2 S1’ S0 O6 = G S2 S1 S0’ O7 = G S2 S1 S0 Demultiplexers/decoders Decoders/demultiplexers: general concept – single data input, n control inputs, 2
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This note was uploaded on 03/04/2012 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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wk3 Lec - CSE140: Components and Design Techniques for...

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