lec17_s09 - ©W\ Cd\_ . . 33.0 00:00:00.0 0.3.03. 8 5.5.0....

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F‘ = A , . 0000 Function 0 No write 0 R1 001 Constath 1 F = A +1 . 0001 ' Data In 1 Write 1 R2 _ 010 ' F = A +3 0010 ' R3 011 F=A+B+1 0011 ‘ R4 100 F = A +§ 0100 'R5 , 101 F_=A+§+1 0101 R6 110 F'.= A - 1 ‘ 0110 R7 111 F = A ' 0111 F = AAB 1000 F = AvB 1001 ’ F = 4693 1010 F g A 1011 F = B~ 1100 F.= SIB 1101' 'F'=VSl-B- 1110 3/30/2001 Address out Data in Data out 1_o 2 B address D data I 8 X n "Registeg file 7 6.5 13’ VDfladdréssA I Constant in' 8 ,- n ____—————+ A address 12 AA 10 15 14 13 12 11' 1o 9 2 Ir M x. H /20 CONTROL WORD B‘US‘lNIG STRATEGIES General strategies. to 'interconnect'registe'rs: _ Opoin't-to-point connections - a path from every possible source ' to every possible destinations , a ,. ' ' thus - a set of interconnection pathways that are shared by - multiple data sources and destinations ' <>a single shared-bus interconnection <’> m'ultiple Special-purpose- buses . ' Ac'ritical design decision H 40 Tradebfi: datapath 8; control V vs, 1 amount of parallelism . - ' complexity ' ' supported by the hardware- , . ,‘ m a . I QC ‘ flit ‘ point-to-point a ' \ . Bus——-~- 2 buses- Mesa): .aalflzsse. -./ ‘ WWI/«u! ‘ yeasgl/ 3/30/9005] . twee. m2¢xamnc-f. ' _ ' ‘ .z i i a ‘3 I: ‘0'.“Pl‘*"l”‘ ._ Cami»; of 303R: caanygp; «xi-gauge cyan-sum. _ E)“: _ ,- I - =36{fi":0}53’01‘ :. Lao-a1: ' ‘ . 3 _ [ya], feud“. at we, Mum. elf-a9; _ 3/36/2009. ' PoINT-to-Pmm-muecnoufs . ' 0 v. N . Rardwm- cod. . s .. *3 _ __ _ 3 . V: Imug It." 13 j a . ‘ ‘ , 5"? q ‘ . «5-. an; @809de P's-"3 A . Hines . -3’-°'-‘9“-‘"a ' ~ 5x2: SWAP-R1 and R2 - ' T 3211:014-01 * - ' ' S1 [1 :014— . ' Lqu—1 ; i LD1 «1, SINGLE BUS _ _The sharedjbus (and its niux) is a critical resource because it can be used by only one transfer" at a time. - ’ _ - But the single source register can broadcast simultaneously to _ more than one destination register. . ' ' 0 lb“ ‘ Instead of a mix foreach reg, a single mux is shared by all regs ‘ Ext:- R0«.R1,R39¥R2_ ./.statex: Sl1=0]‘- 01 R“- N LDO <— 1 a «red: ‘8‘“ ‘state y: sum] «e 10 R3 4- a: .13/30/200‘5 1 I SINGLE Bus To swap, need an extra register, a larger mux, and 3 clock cycles Ex2: ' SWAP R1‘andR2 max: -s[1:01<—o1 } R3,.” 7 - ' ' LD3 <— 1 I 0.5m 3 «5 term " 3 R P ’statey: S[1:0]'+—10 } "‘— “a = LD.1 ‘— 1.' .. ' 3 d“! '5‘“ state 2: s[1:01<— 11 _ Rae—33 LDz s—_ 1 ‘ ISINGLE‘ Bus REGISTER INTERCONNECTION * WITH TRl-STATE 'BUFFERS Uses much less hardware. The decoder guarantees that only 1 regiser is gated onto the bus ow\ow ou\_u_ ma .4 2 E oémtaoo VV . . . _ 3 3 as? 3333 .3 _. 31! as» :13? 3...... {+3 V 52. £_,inna.v33 8“; nu E 5552 .2 35> , 2.3 3 233? 53 av 3.22; 90w. .3 .83 09cm . 7323.3 1.3, :0. 1'5. _ _ _ .Eofimmm .9. EES a. E 5559 E2”. .391 38.63 850$ (m N . *0 «3 59¢ .33... 131 _ _ . 33 3 can»! 3 3* .83 km . V 8.32.» tn .H .. . .... . _ V 1.0:... 3. e. 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lec17_s09 - ©W\ Cd\_ . . 33.0 00:00:00.0 0.3.03. 8 5.5.0....

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