CH7A - Multi-level Gate Circuit M lti l l G t Ci it Hasan...

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Multi-level Gate Circuit Hasan Zidan Department of Electrical Engineering AUST 1
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MULTI-LEVEL GATE NETWORKS The maximum number of gates cascaded in series between a network input and the output is referred to as the umber of vels of gates number of levels of gates . A function written in SOP/POS form corresponds directly to a two-level gate network . We will assume that all variables and their complements are available as network inputs. ( This is usually the case in digital networks where the gates are driven by FF outputs .) Number of levels affects: 1. Number of gates and gate inputs ( cost ) 2. Gate propagation delays 2
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Two Realizations for Z 4 levels 6 gates g 13 gate inputs 3 levels 6 gates 9 ate inputs 3 19 gate inputs
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Ex. Design using AND,OR Gates Problem: Find a network of AND and OR gates to realize f(a,b,c,d) = Σ m(1,5,6,10,13,14) Consider solutions with 2 and 3 gate levels. Try to minimize the number of gates and the total number of gate inputs.) ab 01 00 00 cd 00 11 10 f= a’c’d + bc’d + bcd’ + acd’ 01 01 10 10 Two-level AND-OR 2 levels 5 gates 6 ate inputs 4 16 gate inputs
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Ex. Continued… actoring f = a’ ’ d b ’ d b d’ a Factoring f a c d + b + b c d + c d f = c’ d (a’ + b) + c d’ (a + b) 3 levels ates 5 gates 12 gate inputs * Three-level OR-AND-OR Grouping 0’s on the K-map yields: f’ = c’d’ + ab’c’ + cd + a’b’c f = (c + d)(a’ + b + c)(c’ + d’)(a + b + c’) vels ab 01 0 cd 00 11 10 2 levels 5 gates 14 gate inputs 0 0 00 00 01 0 1 0 0 0 0 5 * Two-level OR-AND 0 1 10 1 1
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factor f’ = c’d’+ ab’c’ + cd + a’b’c
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This note was uploaded on 03/10/2012 for the course ENGINEERIN 131231 taught by Professor Dr.hamad during the Spring '12 term at Amity University.

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CH7A - Multi-level Gate Circuit M lti l l G t Ci it Hasan...

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