# CH7B - Multiplexers Multiplexers Decoders Hasan Zidan...

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ultiplexers Decoders Multiplexers, Decoders Hasan Zidan Department of Electrical Engineering AUST

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When designing a multiple Output Network Try to minimize the total number of gates required If several solutions require the same number of gates, the one with the minimum number of gate inputs should be chosen. 2
Design of Two-Level Multiple-O/p Networks esign a four inputs three outputs which realizes the Design a four inputs, three outputs which realizes the functions F1(A,B,C,D) = Σ m(11,12,13,14,15) = AB + ACD A B C D) = ( 1 2 3 5 ABC’ + CD F2(A,B,C,D) = Σ m(3,7,11,12,13,15) = ABC F3(A,B,C,D) = Σ m(3,7,12,13,14,15) = A’C D + AB 3 AB AB

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Direct Realization (each function as a min. m Product) sum Product) Cost is 9 gates, 21 gate inputs Note: AB is common to F1, F3 = AB+ACD = ABC’+ A’ CD+ A CD Multiple-Output Realization ost ates 8 ate inputs 4 = A’CD+AB Cost is 7 gates, 18 gate inputs
Ex.: Using Common Terms in Multiple O/p d b’ b’c = bd + ab + bc = bc + ab’c’ + abd a’bd = c + f 1 = a’bd + abd + ab’c’ + b’c f 2 = c + a’bd ates 2 ate inputs 5 f 3 = bc + ab’c’ + abd 8 gates, 22 gate inputs

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CH7B - Multiplexers Multiplexers Decoders Hasan Zidan...

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