CH12 - Registers and Counters Hasan Zidan Department of...

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egisters and Counters Registers and Counters Hasan Zidan Department of Electrical Engineering AUST 1
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D-FF Register 0 -> 1 0 -> 1 0 -> 0 0 -> 1 Q 3 Q3 LR Q 2 Q2 Q 1 Q1 Q 0 Q0 D3 CK CLR D2 CK CLR D1 CK CLR D0 CK CLR Clear Clock 1 1 1 0 2
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Binary Counter using T Latch esign is in synchronous form A B C Design is in synchronous form A B C T A T B T C (P) Since a pulse (P) is required to initiate each change of state: T C =1 3 T A = BCP, T B = CP, T C = P =BC =C
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Sequence Generators T Flip-Flop A B C A + B + C + T A T B T C 0 0 0 1 0 0 1 0 0 0 0 1 -- -- -- x x x 000 00 11 0 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 -- -- -- x x 100 111 010 011 1 x 1 1 0 -- -- -- x x x 1 1 1 0 1 0 1 0 1 State Graph 1 1 00 0 1 A BC 1 1 00 0 1 A BC 1 1 00 0 1 A BC Q Q + T 0 0 0 0 1 1 x x 1 01 0 x x 1 01 0 x x 1 01 0 1 1 0 1 1 1 0 4 10 x T A =A’B’+AB =(A’+B)(A+B’) 10 x T B =A’C+AB’ =(A’+B')(A+C) 1 x 10 T C =(A+B)
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Sequence Generators (Cont’d) equence Generator using 5 Sequence Generator using Clocked T-FF’s Timing Diagram
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Sequence Generators using SR-Latch, FF 000 00 11 A B C A + B + C + S A R A S B R B S C R C 0 0 0 1 0 0 1 0 01 -- -- -- x 100 10 011 0 0 1 x 0 1 0 0 1 1 0 X 0 1 1 0 0 0 0 X 1 0 0 1 1 1 X 0 111 010 State Graph 1 0 1 -- -- -- x x 1 1 0 -- -- -- x x 1 1 1 0 1 0 0 1 1 1 00 0 1 A BC x Q Q
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This note was uploaded on 03/10/2012 for the course ENGINEERIN 131231 taught by Professor Dr.hamad during the Spring '12 term at Amity University.

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CH12 - Registers and Counters Hasan Zidan Department of...

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