Execution: The execution component takes the flags from the decoder as well as the values from the register file and uses ALUSRC to select the input value between that of the second input register and imm16, the 16 LSBs of the opcode. The component then does the operation and outputs. Furthermore, if the writeback component detects data hazards in either of the input registers, the execution component will patch in the forwarded value. Since only one register can be updated for each instruction, then data hazard can only occur for a single input register at a time (unless they’re both the same register). For example, in the following code 1 $1 = $2 + $3 2 $2 = $3 + $4 3 $3 = $1 + $2 1 gets computed in the first cycle and its value sits on the pipeline. In the second cycle, 2 gets computed and 1 is pushed onto the memory stage’s pipeline, 2’s value sits on the pipeline of the execution component. In three, assuming that write time into the register file is less than that of
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This note was uploaded on 03/12/2012 for the course CS 3410 taught by Professor Kavitabala during the Spring '08 term at Cornell.