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School Machine Structures (It’s a bit more complicated!) So1ware Hardware • Parallel Requests CS 61C: Great Ideas in Computer Architecture Instruc(ons as Numbers Assigned to computer e.g., Search “Katz” • Parallel Threads Parallelism & Assigned to core e.g., Lookup, Ads Compiler Assembly Language Program (e.g., MIPS) lw
lw
sw
sw Assembler Machine Language Program (MIPS) $t0, 0($2) $t1, 4($2) $t1, 0($2) $t0, 4($2) 0000
1010
1100
0101 1001
1111
0110
1000 1100
0101
1010
0000 Anything can be represented as a number, i.e., data or instrucZons 1010
0000
0101
1100 1111
1001
1000
0110 0101
1100
0000
1010 Cache Memory Today’s • Programming Languages Lecture 2/6/12 Spring 2012
Lecture #7 Logic Gates 2 Review We are here! 0110
1000
1111
1001 Core FuncZonal Unit(s) A0+B0 A1+B1 A2+B2 A3+B3 • Hardware descripZons Big Idea #1: Levels of RepresentaZon/
InterpretaZon temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; Input/Output InstrucZon Unit(s) >1 data item @ one Zme e.g., Add of 4 pairs of words 1 Core Memory (Cache) • Parallel Data Spring 2012
Lecture #7 Computer … Core >1 instrucZon @ one Zme e.g., 5 pipelined instrucZons All gates @ one Zme High Level Language Program (e.g., C) Achieve High Performance • Parallel InstrucZons Instructor: David A. Pa>erson h>p://inst.eecs.Berkeley.edu/~cs61c/sp12 2/6/12 Harness Smart Phone Warehouse Scale Computer 1000
0110
1001
1111 ! Machine Interpreta4on • C is funcZon oriented; code reuse via funcZons – Jump and link (jal) invokes, jump register (jr
$ra) returns – Registers $a0$a3 for arguments, $v0$v1 for return values • Stack for spilling registers, nested funcZon calls, C local (automaZc) variables Hardware Architecture DescripCon (e.g., block diagrams) Architecture Implementa4on 2/6/12 Logic Circuit DescripCon (Circuit SchemaCc Diagrams) Spring 2012
Lecture #7 3 2/6/12 Agenda •
•
•
•
•
• Spring 2012
Lecture #7 4 Key Concepts • Inside computers, everything is a number • But everything is of a ﬁxed size Everything is a Number Administrivia Overﬂow and Real Numbers InstrucZons as Numbers
Assembly Language to Machine Language Summary 2/6/12 Spring 2012
Lecture #7 – 8
bit bytes, 16
bit half words, 32
bit words, 64
bit double words, … • Integer and ﬂoaZng point operaZons can lead to results too big to store within their representaZons: overﬂow/underﬂow 5 2/6/12 Spring 2012
Lecture #7 6 1 2/6/12 Signed and Unsigned Integers Unsigned Integers • C, C++ also have unsigned integers, which are used for addresses • 32
bit word can represent 232 binary numbers • Unsigned integers in 32 bit word represent 0 to 232
1 (4,294,967,295) 0000 0000 0000 0000 0000 0000 0000 0000two = 0ten 0000 0000 0000 0000 0000 0000 0000 0001two = 1ten 0000 0000 0000 0000 0000 0000 0000 0010two = 2ten ... ... 0111 1111 1111 1111 1111 1111 1111 1101two = 2,147,483,645ten 0111 1111 1111 1111 1111 1111 1111 1110two = 2,147,483,646ten 0111 1111 1111 1111 1111 1111 1111 1111two = 2,147,483,647ten 1000 0000 0000 0000 0000 0000 0000 0000two = 2,147,483,648ten 1000 0000 0000 0000 0000 0000 0000 0001two = 2,147,483,649ten 1000 0000 0000 0000 0000 0000 0000 0010two = 2,147,483,650ten ... ... 1111 1111 1111 1111 1111 1111 1111 1101two = 4,294,967,293ten 1111 1111 1111 1111 1111 1111 1111 1110two = 4,294,967,294ten 1111 1111 1111 1111 1111 1111 1111 1111two = 4,294,967,295ten 2/6/12 2/6/12 • C, C++, and Java have signed integers, e.g., 7,
255: int x, y, z; Spring 2012
Lecture #7 9 Signed Integers and Two’s Complement RepresentaZon Sign Bit • Signed integers in C; want ½ numbers <0, want ½ numbers >0, and want one 0 • Two’s complement treats 0 as posiZve, so 32
bit word represents 232 integers from
231 (–2,147,483,648) to 231
1 (2,147,483,647) – Note: one negaZve number with no posiZve version – Book lists some other opZons, all of which are worse – Every computers uses two’s complement today • Most signiﬁcant bit (levmost) is the sign bit, since 0 means posiZve (including 0), 1 means negaZve – Bit 31 is most signiﬁcant, bit 0 is least signiﬁcant 2/6/12 Spring 2012
Lecture #7 11 0 to +31 ☐ Two’s Complement Integers 0000 0000 0000 0000 0000 0000 0000 0000two = 0ten 0000 0000 0000 0000 0000 0000 0000 0001two = 1ten 0000 0000 0000 0000 0000 0000 0000 0010two = 2ten ... ... 0111 1111 1111 1111 1111 1111 1111 1101two = 2,147,483,645ten 0111 1111 1111 1111 1111 1111 1111 1110two = 2,147,483,646ten 0111 1111 1111 1111 1111 1111 1111 1111two = 2,147,483,647ten 1000 0000 0000 0000 0000 0000 0000 0000two = –2,147,483,648ten 1000 0000 0000 0000 0000 0000 0000 0001two = –2,147,483,647ten 1000 0000 0000 0000 0000 0000 0000 0010two = –2,147,483,646ten ... ... 1111 1111 1111 1111 1111 1111 1111 1101two = –3ten 1111 1111 1111 1111 1111 1111 1111 1110two = –2ten 1111 1111 1111 1111 1111 1111 1111 1111two = –1ten 2/6/12 Spring 2012
Lecture #7 12 • Useful to operate on ﬁelds of bits within a word − e.g., characters within a word (8 bits) • OperaZons to pack /unpack bits into words • Called logical opera(ons
32 to +31 ☐ 10 MIPS Logical InstrucZons Suppose we had a 5 bit word. What integers can be represented in two’s complement? ☐ Spring 2012
Lecture #7
16 to +15! ☐ 13 Logical
C
Java
MIPS
operations operators operators instructions
and
&
&
Bitbybit AND
or


Bitbybit OR
nor
~
~
Bitbybit NOT
sll
<<
<<
Shift left
srl
>>
>>>
Shift right 2/6/12 Spring 2012
Lecture #7 15 2 2/6/12 Bit
by
bit DeﬁniZon OperaCon Input Input AND 0 0 0 AND 0 1 0 AND 1 0 0 AND 1 1 1 OR 0 0 0 OR OR 0 1 1 0 Examples Output 1 1 OR 1 1 0 0 1 NOR 0 1 0 NOR 2/6/12 1 NOR 1 0 0 NOR 1 Spring 2012
Lecture #7 1 0 • If register $t2 contains and 0000 0000 0000 0000 0000 1101 1100 0000two • Register $t1 contains 0000 0000 0000 0000 0011 1100 0000 0000two • What is value of $t0 aver: and $t0,$t1,$t2 # reg $t0 = reg $t1 & reg $t2 16 2/6/12 Spring 2012
Lecture #7 Student Roule>e? 17 Examples Examples • If register $t2 contains and 0000 0000 0000 0000 0000 1101 1100 0000two • Register $t1 contains 0000 0000 0000 0000 0011 1100 0000 0000two • What is value of $t0 aver: or $t0,$t1,$t2 # reg $t0 = reg $t1  reg $t2 • If register $t2 contains and 0000 0000 0000 0000 0000 1101 1100 0000two • Register $t1 contains 0000 0000 0000 0000 0011 1100 0000 0000two • What is value of $t0 aver: nor $t0,$t1,$zero # reg $t0 = ~ (reg $t1  0) 2/6/12 2/6/12 Spring 2012
Lecture #7 Student Roule>e? 19 Shiving Spring 2012
Lecture #7 Student Roule>e? 21 Shiving • Shiv lev logical moves n bits to the lev (insert 0s into empty bits) – Same as mulZplying by 2n for two’s complement number • For example, if register $s0 contained • Shiv right arithmeZc moves n bits to the right (insert high order sign bit into empty bits) • For example, if register $s0 contained 0000 0000 0000 0000 0000 0000 0001 1001two= 25ten 0000 0000 0000 0000 0000 0000 0000 1001two= 9ten • If executed sra $s0, $s0, 4, result is: • If executed sll $s0, $s0, 4, result is: 0000 0000 0000 0000 0000 0000 1001 0000two= 144ten • And 9ten × 2ten4 = 9ten × 16ten = 144ten • Shiv right logical moves n bits to the right (insert 0s into empty bits) – NOT same as dividing by 2n (negaZve numbers fail) 2/6/12 Spring 2012
Lecture #7 23 2/6/12 Spring 2012
Lecture #7 Student Roule>e? 24 3 2/6/12 Impact of Signed and Unsigned Integers on InstrucZon Sets Shiving • Shiv right arithmeZc moves n bits to the right (insert high order sign bit into empty bits) • For example, if register $s0 contained • What (if any) instrucZons aﬀected? – Load word, store word? – branch equal, branch not equal? – and, or, sll, srl? – add, sub, mult, div? – slZ (set less than immediate)? 1111 1111 1111 1111 1111 1111 1110 0111two=
25ten • If executed sra $s0, $s0, 4, result is: 2/6/12 Spring 2012
Lecture #7 Student Roule>e? 26 ☐ ☐ •
•
•
• Logical operaZons AND and OR do & and  while condiZonal branches do && and  The previous statement has it backwards: && and  logical ops, & and  are branches They are redundant and mean the same thing: && and  are simply inherited from the programming language B, the predecessor of C! 2/6/12 2009 Spring 2011
Lecture #13 28 Lab #4 posted Project #1 Due Sunday @ 11:59:59 This week should be easier Midterm is now on the horizon: 2/6/12 1999 • 2 to 3 Zmes/year spend weekend with old friends I went to high school (South Torrance) with to play poker, watch Superbowl, go bodysurﬁng, talk about life 1974 Student Roule>e? – No discussion during exam week – TA Review: Su, Mar 4, starZng 2 PM, 2050 VLSB – Exam: Tu, Mar 6, 6:40
9:40 PM, 2050 VLSB (room change) – Small number of special consideraZon cases, due to class conﬂicts, etc.—contact me 29 Ge~ng to Know Profs: My Old Friends Spring 2012
Lecture #7 Administrivia C provides two sets of operators for AND (& and &&) and two sets of operators for OR ( and ) while MIPS doesn’t. Why? ☐ 2/6/12 Old friends even more 32 valuable as you age Spring 2012
Lecture #7 31 Agenda •
•
•
•
•
•
• Everything is a Number Administrivia Overﬂow and Real Numbers InstrucZons as Numbers Technology Break Assembly Language to Machine Language Summary 2/6/12 Spring 2012
Lecture #7 33 4 2/6/12 Goals for FloaZng Point ScienZﬁc NotaZon (e.g., Base 10) • Standard arithmeZc for reals for all computers • Normalized scien(ﬁc nota(on (aka standard form or exponen(al nota(on): – Like two’s complement • Keep as much precision as possible in formats • Help programmer with errors in real arithmeZc – r x Ei, E is exponent (usually 10), i is a posiZve or negaZve integer, r is a real number ≥ 1.0, < 10 – Normalized => No leading 0s – 61 is 6.10 x 102, 0.000061 is 6.10 x10
5 – +∞,
∞, Not
A
Number (NaN), exponent overﬂow, exponent underﬂow • Keep encoding that is somewhat compaZble with two’s complement – E.g., 0 in Fl. Pt. is 0 in two’s complement – Make it possible to sort without needing to do ﬂoaZng point comparison 2/6/12 Spring 2012
Lecture #7 34 • r x Ei, E where is exponent, i is a posiZve or negaZve integer, r is a real number ≥ 1.0, < 10 2/6/12 • (r x ei) x (s x ej) = (r x s) x ei+j (1.999 x 102) x (5.5 x 103) = (1.999 x 5.5) x 105 = 10.9945 x 105 = 1.09945 x 106 • (r x ei) / (s x ej) = (r / s) x ei
j (1.999 x 102) / (5.5 x 103) = 0.3634545… x 10
1 = 3.634545… x 10
2 • For addiZon/subtracZon, you ﬁrst must align: (1.999 x 102) + (5.5 x 103) = (.1999 x 103) + (5.5 x 103) = 5.6999 x 103 Spring 2012
Lecture #7 35 Which is Less? (i.e., closer to
∞) ScienZﬁc NotaZon (e.g., Base 10) 2/6/12 Spring 2012
Lecture #7 36 • 0 vs. 1 x 10
127? • 1 x 10
126 vs. 1 x 10
127? •
1 x 10
127 vs. 0? •
1 x 10
126 vs.
1 x 10
127? 2/6/12 FloaZng Point: RepresenZng Very Small Numbers Spring 2012
Lecture #7 Student Roule>e? 37 Bias NotaZon (+127) • Zero: Bit pa>ern of all 0s is encoding for 0.000 ⇒ But 0 in exponent should mean most negaZve exponent (want 0 to be next to smallest real) ⇒ Can’t use two’s complement (1000 0000two) How it is interpreted How it is encoded ∞, NaN • Bias nota(on: subtract bias from exponent – Single precision uses bias of 127; DP uses 1023 • 0 uses 0000 0000two => 0
127 =
127; ∞, NaN uses 1111 1111two => 255
127 = +128 – Smallest SP real can represent: 1.00…00 x 2
126 – Largest SP real can represent: 1.11…11 x 2+127 2/6/12 Spring 2012
Lecture #7 Ge~ng closer to zero Zero 39 2/6/12 Spring 2012
Lecture #7 40 5 2/6/12 What If OperaZon Result Doesn’t Fit in 32 Bits? Depends on the Programming Language • Overﬂow: calculate too big a number to represent within a word • Unsigned numbers: 1 + 4,294,967,295 (232
1) • Signed numbers: 1 + 2,147,483,647 (231
1) • C unsigned number arithmeZc ignores overﬂow (arithmeZc modulo 232) 2/6/12 2/6/12 Spring 2012
Lecture #7 41 1 + 4,294,967,295 = Depends on the Programming Language Student Roule>e? 42 • Other languages want overﬂow signal on signed numbers (e.g., Fortran) • What’s a computer architect to do? 1 + 2,147,483,647 (231
1) = Spring 2012
Lecture #7 Student Roule>e? Depends on the Programming Language • C signed number arithmeZc also ignores overﬂow 2/6/12 Spring 2012
Lecture #7 43 MIPS SoluZon: Oﬀer Both 2/6/12 Spring 2012
Lecture #7 44 What About Real Numbers in Base 2? • InstrucZons that can trigger overﬂow: • r x Ei, E where is exponent (2), i is a posiZve or negaZve integer, r is a real number ≥ 1.0, < 2 • Computers version of normalized scienZﬁc notaZon called Floa(ng Point notaZon – add, sub, mult, div, addi, multi, divi • InstrucZons that don’t overﬂow are called “unsigned” (really means “no overﬂow”): – addu, subu, multu, divu, addiu, multiu, diviu • Given semanZcs of C, always use unsigned versions • Note: slt and slti do signed comparisons, while sltu and sltiu do unsigned comparisons – Nothing to do with overﬂow – When would get diﬀerent answer for slt vs. sltu? 2/6/12 Spring 2012
Lecture #7 Student Roule>e? 45 2/6/12 Spring 2012
Lecture #7 46 6 2/6/12 FloaZng Point Numbers FloaZng Point Numbers • What about bigger or smaller numbers? • IEEE 754 FloaZng Point Standard: Double Precision (64 bits) • 32
bit word has 232 pa>erns, so must be approximaZon of real numbers ≥ 1.0, < 2 • IEEE 754 FloaZng Point Standard: – 1 bit for sign (s) of ﬂoaZng point number – 8 bits for exponent (E) – 23 bits for frac(on (F) (get 1 extra bit of precision if leading 1 is implicit) (
1)s x (1 + F) x 2E • Can represent from 2.0 x 10
38 to 2.0 x 1038 2/6/12 Spring 2012
Lecture #7 47 More FloaZng Point – 1 bit for sign (s) of ﬂoaZng point number – 11 bits for exponent (E) – 52 bits for frac(on (F) (get 1 extra bit of precision if leading 1 is implicit) (
1)s x (1 + F) x 2E • Can represent from 2.0 x 10
308 to 2.0 x 10308 • 32 bit format called Single Precision 2/6/12 Spring 2012
Lecture #7 48 FloaZng Point Add AssociaZvity? • What about 0? • What if do something stupid? (∞ – ∞, 0 ÷ 0) • A = (1000000.0 + 0.000001)
1000000.0 • B = (1000000.0
1000000.0) + 0.000001 • In single precision ﬂoaZng point arithmeZc, A does not equal B • What if result is too big? (2x10308 x 2x102) • FloaZng Point AddiZon is not AssociaZve! – Bit pa>ern all 0s means 0, so no implicit leading 1 • What if divide 1 by 0? – Can get inﬁnity symbols +∞,
∞ – Sign bit 0 or 1, largest exponent, 0 in fracZon – Can get special symbols NaN for Not
a
Number – Sign bit 0 or 1, largest exponent, not zero in fracZon A = 0.000000, B = 0.000001 – Get overﬂow in exponent, alert programmer! – Integer addiZon is associaZve • What if result is too small? (2x10
308 ÷ 2x102) • When does this ma>er? – Get underﬂow in exponent, alert programmer! 2/6/12 Spring 2012
Lecture #7 49 2/6/12 Spring 2011
Lecture #8 MIPS FloaZng Point InstrucZons MIPS FloaZng Point InstrucZons • C, Java has single precision (float) and double precision (double) types • MIPS instrucZons: .s for single, .d for double 50 • C, Java has single precision (float) and double precision (double) types • MIPS instrucZons: .s for single, .d for double – Fl. Pt. AddiZon single precision: Fl. Pt. AddiZon double precision: – Fl. Pt. SubtracZon single precision: Fl. Pt. SubtracZon double precision: – Fl. Pt. MulZplicaZon single precision: Fl. Pt. MulZplicaZon double precision: – Fl. Pt. Divide single precision: Fl. Pt. Divide double precision: 2/6/12 Spring 2012
Lecture #7 Student Roule>e? – Fl. Pt. AddiZon single precision: add.s Fl. Pt. AddiZon double precision: add.d – Fl. Pt. SubtracZon single precision: sub.s Fl. Pt. SubtracZon double precision: sub.d – Fl. Pt. MulZplicaZon single precision: mul.s Fl. Pt. MulZplicaZon double precision: mul.d – Fl. Pt. Divide single precision: div.s Fl. Pt. Divide double precision: div.d 51 2/6/12 Spring 2012
Lecture #7 52 7 2/6/12 MIPS FloaZng Point InstrucZons Peer InstrucZon QuesZon • C, Java have single precision (float) and double precision (double) types • MIPS instrucZons: .s for single, .d for double – Fl. Pt. Comparison single precision: Fl. Pt. Comparison double precision: – Fl. Pt. branch: • Since rarely mix integers and FloaZng Point, MIPS has separate registers for ﬂoaZng
point operaZons: $f0, $f1, …, $f31
– Double precision uses adjacent even
odd pairs of registers: – $f0 and $f1, $f2 and $f3, $f4 and $f5, …, $f30 and $f31 • Need data transfer instrucZons for these new registers – lwc1 (load word), swc1 (store word) – Double precision uses two lwc1 instrucZons, two swc1 instrucZons 2/6/12 Spring 2012
Lecture #7 53 ☐ ☐ 2/6/12 Spring 2012
Lecture #7 54 Pi†alls C provides two sets of operators for AND (& and &&) and two sets of operators for OR ( and ) while MIPS doesn’t. Why? ☐ Suppose Big, Tiny, and BigNegaZve are ﬂoats in C, with Big iniZalized to a big number (e.g., age of universe in seconds or 4.32 x 1017), Tiny to a small number (e.g., seconds/
femtosecond or 1.0 x 10
15), BigNegaZve =
Big. Here are two condiZonals: I. (Big * Tiny) * BigNegaZve == (Big * BigNegaZve) * Tiny II. (Big + Tiny) + BigNegaZve == (Big + BigNegaZve) + Tiny Which statement about these is correct? Orange. I. is false and II. is false Green. I. is false and II. is true Pink. I. is true and II. is false Yellow. I. is true and II. is true • FloaZng point addiZon is NOT associaZve • Some opZmizaZons can change order of ﬂoaZng point computaZons, which can change results • Need to ensure that ﬂoaZng point algorithm is correct even with opZmizaZons Logical operaZons AND and OR do & and  while condiZonal branches do && and  The previous statement has it backwards: && and  logical ops, & and  are branches They are redundant and mean the same thing: && and  are simply inherited from the programming language B, the predecessor of C!
55 2/6/12 Spring 2012
Lecture #7 57 Key Concepts InstrucZons as Numbers • MIPS ISA guided by four RISC design principles: • InstrucZons are also kept as binary numbers in memory 1.
2.
3.
4. 2/6/12 Simplicity favors regularity Smaller is faster Make the common case fast Good design demands good compromises Spring 2012
Lecture #7 – Stored program concept – As easy to change programs as it is to change data • Register names mapped to numbers • Need to map instrucZon operaZon to a part of number 58 2/6/12 Spring 2012
Lecture #7 59 8 2/6/12 InstrucZons as Numbers InstrucZons as Numbers • addu $t0,$s1,$s2 • sll $zero,$zero,0 – DesZnaZon register $t0 is register 8 – Source register $s1 is register 17 – Source register $s2 is register 18 – Add unsigned instrucZon encoded as number 33 0 17 000000 10001 18 8 0 – $zero is register 0 – Shiv amount 0 is 0 – Shiv lev logical instrucZon encoded as number 0 33 0 10010 01000 00000 100001 6 b its 5 bits 5 bits 5 bits 5 bits 6 bits • Groups of bits call ﬁelds (unused ﬁeld default is 0) • Layout called instruc(on format • Binary version called machine instruc(on 2/6/12 Spring 2012
Lecture #7 6 bits 60 Student Roule>e? op rs rt rd shamt 5 bits 5 bits 5 bits 2/6/12 62 5 bits 5 bits 6 bits 2/6/12 Spring 2012
Lecture #7 61 2/6/12 Spring 2012
Lecture #7 Student Roule>e? 63 What about Load, Store, Immediate, Branches, Jumps? 6 bits Spring 2012
Lecture #7 5 bits – Invented about 1947 (many claim invenZon) • Fields for constants only 5 bits (
16 to +15) op: Basic operaZon of instrucZon, or opcode rs: 1st register source operand rt: 2nd register source operand. rd: register desZnaZon operand (result of operaZon) • shamt: Shiv amount. • funct: FuncZon. This ﬁeld, oven called func(on code, selects the speciﬁc variant of the operaZon in the op ﬁeld •
•
•
• 0 • As easy to change programs as to change data! • ImplicaZons? funct 5 bits 0 • Stored program concept Names of MIPS ﬁelds 6 bits 0 ImplicaZons of Everything is a Number • Up to program to decide what data means • Example 32
bit data shown as binary number: 0000 0000 0000 0000 0000 0000 0000 0000two What does it mean if its treated as 1. Signed integer 2. Unsigned integer 3. FloaZng point 4. ASCII characters 5. Unicode characters 6. MIPS instruc(on Spring 2012
Lecture #7 5 bits 0 00000 00000 00000 000000 • Can also represent machine code as base 16 or base 8 number: 0000 0000hex, 0000000000oct Everything in a Computer is Just a Binary Number 2/6/12 0 000000 00000 64 – Too small for many common cases • #1 Simplicity favors regularity (all instrucZons use one format) vs. #3 Make common case fast (mulZple instrucZon formats)? • 4th Design Principle: Good design demands good compromises • Be>er to have mulZple instrucZon formats and keep all MIPS instrucZons same size – All MIPS instrucZons are 32 bits or 4 bytes 2/6/12 Spring 2012
Lecture #7 65 9 2/6/12 Register (R), Immediate (I), Jump (J) InstrucZon Formats Names of MIPS Fields in I
type op rs rt address or constant 6 bits 5 bits 5 bits 16 bits • op: Basic operaZon of instrucZon, or opcode • rs: 1st register source operand • rt: 2nd register source operand for branches but register desZnaZon operand for lw, sw, and immediate operaZons • Address/constant: 16
bit two’s complement number rs rt rd shamt funct 5 bits 5 bits 5 bits 5 bits 6 bits I
type op rs rt address or constant 6 bits 5 bits 5 bits 16 bits • Now loads, stores, branches, and immediates can have 16
bit two’s complement address or constant:
32,768 (
215) to +32,767 (215
1) • What about jump, jump and link? J
type – Note: equal in size of rd, shamt, funct ﬁelds 2/6/12 op 6 bits R
type op address 6 bits Spring 2012
Lecture #7 66 26 bits 2/6/12 Spring 2012
Lecture #7 Encoding of MIPS InstrucZons: Must Be Unique! 67 Agenda InstrucZon For
mat op rs rt rd shamt funct address addu subu sltu sll addi unsigned lw (load word) sw (store word) beq bne j ( jump) jal jr ( jump reg) R R R R I I I I I J J R 0 0 0 0 9ten 35ten 43ten 4ten 5ten 2ten 3ten 0 reg reg reg reg reg reg reg reg reg reg reg reg reg reg reg reg 0 0 0 constant 33ten 35ten 43ten 0ten n.a. reg reg reg reg reg n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. constant address address address address address address reg reg reg 0 8ten n.a. 2/6/12 n.a n.a. n.a. n.a. Spring 2012
Lecture #7 68 ConverZng C to MIPS Machine code &A=$t0 (reg 8), $t1 (reg 9), h=$s2 (reg 18) •
•
•
•
•
• Everything is a Number Administrivia Overﬂow and Real Numbers InstrucZons as Numbers Assembly Language to Machine Language Summary 2/6/12 Spring 2012
Lecture #7 ConverZng C to MIPS Machine code &A=$t0 (reg 8), $t1 (reg 9), h=$s2 (reg 18) A[300] = h + A[300]; Format? lw $t0,1200($t1) _ A[300] = h + A[300]; Format? lw $t0,1200($t1) _ 35 addu $t1,$s2,$t0 sw $t0,1200($t1) addu $t1,$s2,$t0 sw $t0,1200($t1) InstrucZon For
mat addu R lw (load word) I sw (store word) I 2/6/12 R
type I
type J
type _ _ op rs rt rd shamt funct address 0 35ten 43ten reg reg reg reg reg reg reg 0 33ten n.a. n.a. n.a. n.a. n.a. n.a. n.a. address address op op op rs rs rt rt Spring 2012
Lecture #7 rd shamt funct address or constant address Student Roule>e? 70 69 InstrucZon For
mat addu R lw (load word) I sw (store word) I 2/6/12 R
type I
type J
type _ 0 9 18 8 8 _ 43 9 8 9 1200 0 33 1200 op rs rt rd shamt funct 0 35ten 43ten reg reg reg reg reg reg reg 0 33ten n.a. n.a. n.a. n.a. n.a. n.a. n.a. address address op op op rs rs rt rt Spring 2012
Lecture #7 address rd shamt funct address or constant address 71 10 2/6/12 Addressing in Branches I
type op rs rt address or constant 6 bits 5 bits 5 bits Addressing in Branches 16 bits I
type • Programs much bigger than 216 bytes, but branch address must ﬁt in 16
bit ﬁeld – Must specify a register for branch addresses for big programs: PC = Register + Branch address – Which register? • CondiZonal branching for IF
statement, loops – Tend to be near branches; ½ within 16 instrucZons • Idea: PC
rela(ve branching 2/6/12 Spring 2012
Lecture #7 72 op 26 bits • Same trick for Jumps, Jump and Link PC = Jump address * 4 • Since PC = 32 bits, and Jump address * 4 = 28 bits, what about other 4 bits? • Jump and Jump and Link only changes bo>om 28 bits of PC 2/6/12 Spring 2012
Lecture #7 16 bits Spring 2012
Lecture #7 73 Format? _ 800 sll $t1,$s3,2 addu $t1,$t1,$s6 _ 804 808 lw $t0,0($t1) _ 812 bne $t0,$s5, Exit _ 816 addiu $s3,$s3,1 820 j Loop Exit: 74 32 bit Constants in MIPS R
type I
type J
type op op op _ _ rs rs rt rt Spring 2012
Lecture #7 rd shamt funct address or constant address Student Roule>e? 75 “And in Conclusion, …” • Can create a 32
bit constant from two 32
bit MIPS instrucZons • Load Upper Immediate (lui or “Louie”) puts 16 bits into upper 16 bits of desZnaZon register • MIPS to load 32
bit constant into register $s0? 0000 0000 0011 1101 0000 1001 0000 0000two lui $s0, 61 # 61 = 0000 0000 0011 1101two ori $s0, $s0, 2304 # 2304 = 0000 1001 0000 0000two Spring 2012
Lecture #7 address or constant 2/6/12 2/6/12 2/6/12 rt 5 bits • Hardware increments PC early, so relaZve address is PC = (PC + 4) + Branch address • Another opZmizaZon since all MIPS instrucZons 4 bytes long? • MulZply value in branch address ﬁeld by 4! • MIPS PC
relaZve branching PC = (PC + 4) + (Branch address*4) Add Loop: ress address 6 bits rs 5 bits ConverZng to MIPS Machine code Addressing in Jumps J
type op 6 bits 77 • Program can interpret binary number as unsigned integer, two’s complement signed integer, ﬂoaZng point number, ASCII characters, Unicode characters, … • Integers have largest posiZve and largest negaZve numbers, but represent all in between – Two’s comp. weirdness is one extra negaZve numInteger and ﬂoaZng point operaZons can lead to results too big to store within their representaZons: overﬂow/underﬂow • FloaZng point is an approximaZon of reals • Everything is a (binary) number in a computer – InstrucZons and data; stored program concept 2/6/12 Spring 2012
Lecture #7 78 11 ...
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 Spring '08
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