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Unformatted text preview: c A.H.Dixon CMPT 250 : Week 2 (Sept 1317 5 Other ways to provide a behavioral description for Example 1.1 are: As a State Transition Diagram : Each transition arrow is labelled by the binary sequences that will result in that particular transition occurring. The transition arrows are also labelled by a binary sequence that defines the output that should occur when the machine enters the state to which the transition arrow points. SG up c z 2 3 1 C = 1 1 1 1 As a Function Select Table : Rather than tabulate all possible assignments of values to the inputs for each state (as is done in the statetransition and characteristic tables), each row identifies descriptively what behavior should be observed for every possible assignment of values to the control inputs only. To illustrate, Example 1.1 can be defined as follows: SG up c z Ctrl Inputs C up Function ↑ state + ← state if state = 0 then z = 1 else z = 0 ↑ 1 state + ← ( state + 1) mod 4 if state = 0 then z = 1 else z = 0 c A.H.Dixon CMPT 250 : Week 2 (Sept 1317 6 As a State Machine Diagram (SMD) : SMD’s are really just state transition diagrams where additional labels, called “Asserted Outputs” , are attached to the states, and where the inputs are defined by Boolean Expressions, called “Transition Conditions”, rather than by binary sequences. • Transition Condition: A Boolean function of the input variables with the property that it is “true” only for any assignment of values to the input variables that results in the transition along the “arrow” that is being labelled. • Asserted Outputs: A list of all output variables that are to be asserted (that is, set to ’1’). By inference, those variables not included in the list are assumed to be set to ’0’. As well the list includes any register transfers that are to take place in the datapath while the machine is in the state being labelled. Example 1.1 can be expressed as follows: SG up c z up 2 3 1 C = up z up up up up up up In hardware description language (HDL) : A hardware description language is one where the entity definition and the func tional specification can be expressed in formal textual notation, much as algorithms can be expressed in programming languages. Example 1.1 can be expressed in the hardware description language, VHDL, as follows: entity SG is port(C, up : in std_logic; z : out std_logic); end SG; architecture behav of SG is begin process is variable state : integer := 0; c A.H.Dixon CMPT 250 : Week 2 (Sept 1317 7 begin State Transition Function: if C = ’1’ then if up = ’1’ then state := (state + 1) mod 4; end if; end if; Output Function if state = 0 then z <= ’1’; else z <= ’0’; end if; wait on C; end process; 3 VHDL: A NOTATION SYSTEM FOR HARDWARE MODELS VHDL is a language for describing electronic systems, either in terms of their behavior...
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 Spring '09
 DIXON

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