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Week4-103 - c A.H.Dixon 8.2 CMPT 250 Week 4(Sept 27 Oct 1...

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c A.H.Dixon CMPT 250 : Week 4 (Sept 27 - Oct 1) 18 8.2 Implementing an SMD in VHDL There are a number of ways to express a behavioral description in VHDL. The following method uses the information provided in the state machine diagram (SMD) to define two processes: one that describes the state transitions of the SMD, and one that summarizes the Asserted Outputs of the SMD. Since there will be two processes in the architecture, it is helpful to view each process as a separate “component” with both components running in parallel. Each process will need to communicate with the other. The Asserted Outputs process will need to know the latest state of the state transition process. And, the state tran- sition process must decide on the next state based on the latest values of any registers changed by the asserted outputs. Therefore the architecture will require additional sig- nal variables besides those declared in the entity definition to allow the two processes access to information determined by the other. In the following implementation, the state computed by the state transition process will be passed to the asserted outputs process vis the signal variable “ new state ”. At the same time, the asserted outputs process will place on the signal variable “ agt0 ” the value ‘1’ if register A > 0, and place ‘0’ on that signal variable otherwise. The result of this approach is the following: 1. The “state transition ” process only determines the next state. No other calcu- lations are performed. In effect, it is an implementation of the state transition diagram and uses only information provided in the transition condition labels on the transition arrows of the SMD. 2. The “asserted outputs” process simply lists the asserted outputs for each state as specified in the SMD. It provides no information about state transitions. The resulting VHDL source code is as follows: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity MPY4 is port(clk, mpy : in std_logic; d1, d2 : in std_logic_vector(3 downto 0); prod : out std_logic_vector(7 downto 0); rdy : out std_logic); end MPY4; architecture behav of MPY4 is type state is (S0, S1, S2, S3); signal new_state : state; signal agt0 : std_logic; begin -- State Transition Process: process is
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c A.H.Dixon CMPT 250 : Week 4 (Sept 27 - Oct 1) 19 variable curr_state : state := S0; begin if clk = ’1’ then case curr_state is when S0 => if mpy = ’1’ then curr_state := S1; end if; when S1 => if agt0 = ’1’ then curr_state := S2; else curr_state := S3; end if; when S2 => curr_state := S1; when S3 => if mpy = ’0’ then curr_state := S0; end if; end case; end if; new_state <= curr_state; wait on clk; end process; -- Asserted Outputs Process: process is variable rdy_val, agt0_val : std_logic; variable A : std_logic_vector(3 downto 0); variable P, B, prod_val : std_logic_vector(7 downto 0); begin if clk = ’1’ then rdy_val := ’0’; case new_state is when S0 => A := d1; agt0_val := A(0) or A(1) or A(2) or A(3); B := X"0" & d2; P := X"00"; rdy_val := ’1’; when S2 => P := P + B; A := A - X"1"; agt0_val := A(0) or A(1) or A(2) or A(3); when S3 => prod_val := P; rdy_val := ’1’; when others => end case; end if; prod <= prod_val;
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