SampleTest1B-101SOLN

SampleTest1B-101SOLN - NAME: Student Number: 4 pages 1 CMPT...

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NAME: Student Number: 1 4 pages CMPT 250: Sample Test 1(B) 30 marks Answer all questions on the test paper. Use the backs of the pages for rough work, if necessary. Be sure your name and student number are on all pages. A VHDL summary sheet is provided. CAUTION: In accordance with the Academic Honesty Policy (T10.02), academic dishonesty in any form will not be tolerated. 1. The following diagram provides the state machine diagram for a synchronous sequential digital system: ld S0 S1 S2 S3 st st r r mfc mfc mout req, cs rdy (a) List the output conditions defined by this SMD. (2 marks) SOLUTION: rdy, ld, req, cs, mout (b) List the transition conditions defined by this SMD. (3 marks) SOLUTION: st, not st, r, not r, mfc, not mfc
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NAME: Student Number: 2 (c) In VHDL provide a behavioral description for this device. (8 marks) entity Q1 is port( clk, st, r, mfc : in std_logic; rdy, ld, req, cs, mout : out std_logic); end Q1; architecture behav of Q1 is begin process is variable state std_logic_vector(1 downto 0) := "00";
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This note was uploaded on 03/16/2012 for the course ENSC 802 taught by Professor Ivanbaijic during the Spring '12 term at Simon Fraser.

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SampleTest1B-101SOLN - NAME: Student Number: 4 pages 1 CMPT...

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