ASMvhdlTransparencies

ASMvhdlTransparencies - ASMManualAssign.vhd: LIBRARY ieee ;...

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Unformatted text preview: ASMManualAssign.vhd: LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY ASMManualAssign IS PORT ( Clock, Resetn, InBit, BufFull : IN STD_LOGIC ; state : BUFFER STD_LOGIC_Vector (1 DOWNTO 0); CountEN, RegLD, OutFlag : OUT STD_LOGIC ) ; END ASMManualAssign ; ARCHITECTURE ASMArch OF ASMManualAssign IS SIGNAL StateA, StateB, StateC, StateD : STD_LOGIC; BEGIN PROCESS ( Resetn, Clock ) -- state transitions BEGIN IF Resetn = '0' THEN state <= "10" ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE state IS WHEN "10" => IF InBit = '0' THEN state <= "11" ; ELSE state <= "00" ; END IF ; WHEN "11" => state <= "10"; 2 WHEN "00" => IF BufFull = '0' THEN state <= "00"; ELSE state <= "01"; END IF ; WHEN "01" => state <= "10"; WHEN OTHERS => state <= "10"; END CASE ; END IF ; END PROCESS ; -- Conditional and unconditional outputs StateA <= '1' WHEN state = "10" ELSE '0'; StateB <= '1' WHEN state = "11" ELSE '0'; StateC <= '1' WHEN state = "00" ELSE '0'; StateD <= '1' WHEN state = "01" ELSE '0'; CountEN <= StateA OR (StateC AND BufFull); RegLD <= StateA OR StateC; OutFlag <= StateD; END ASMArch ; 3 4 ASMManualAssignGood.vhd LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY ASMManualAssignGood IS PORT (...
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ASMvhdlTransparencies - ASMManualAssign.vhd: LIBRARY ieee ;...

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