EEL4712T1Fall09 - EEL 4712 Digital Design Test 1 Fall...

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EEL 4712 – Digital Design Test 1 – Fall Semester 2009 Name _______________________ 1 1. VHDL Analysis (timing diagrams): Given the following VHDL specification, complete the following timing diagram for outputs Z(0), Z(1), Z(2), Z(3). LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Prob1 IS PORT ( D, CLOCK, CLR1, CLR2 : IN STD_LOGIC ; Z : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END Prob1 ; ARCHITECTURE P1Arch OF Prob1 IS BEGIN PROCESS (CLOCK, CLR1) BEGIN IF CLR1 = '0' THEN Z(0) <= '0'; ELSIF CLOCK'EVENT AND CLOCK='1' THEN IF CLR2 = '0' THEN Z(0) <= '0'; ELSE Z(0) <= D; END IF; END IF; END PROCESS; PROCESS (D,CLOCK) BEGIN IF CLOCK='1' THEN Z(1) <= D; END IF; END PROCESS; PROCESS (D, CLOCK) BEGIN IF CLOCK='1' THEN Z(2) <= D; ELSE Z(2) <= ‘0’; END IF; END PROCESS; PROCESS (CLOCK) BEGIN IF CLOCK'EVENT AND CLOCK='1' THEN Z(3) <= D; END IF; END PROCESS; END P1Arch ; . 16 pts. Important Note: Every flip-flop and latch starts off with an unknown value. Please show propagation delays. Problem 1 D Z(1) Z(2) Z(3) RESETn Z(0) CLR1 CLR2 CLOCK IMPORTANT: Throughout this test, please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed to be wrong.
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EEL 4712 – Digital Design Test 1 – Fall Semester 2009 Name _______________________ 2 2(a). Using the GENERIC feature of VHDL, complete the following code that will define a “generic” component named nBitAdd shown below. The generic component is a n-bit, ripple-carry adder containing “n” full adders. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY nBitAdd IS END nBitAdd; ARCHITECTURE genericAdder OF nBitAdd IS SIGNAL BEGIN PROCESS ( ) -- Hint: Use FOR loop; END PROCESS; END genericAdder; A B Cin S Cout n n nBitAdd n Equations for a full adder: S <= A XOR B XOR Cin; Cout <= (A AND B) OR ((A OR B) AND Cin); Problem 2 15 pts.
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EEL 4712 – Digital Design Test 1 – Fall Semester 2009 Name _______________________ 3 2(b). Given the following ENTITY definition, give me the PORT MAP statement that will create a 32-bit adder using the above generic adder. ENTITY TestGenAdd IS PORT( Cin : IN STD_LOGIC; x, y : IN STD_LOGIC_VECTOR(31 DOWNTO 0); Cout: OUT STD_LOGIC; sumOut: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END TestGenAdd ; Put the PORT MAP statement here: Shown below is the desired timing of a 2-bit counter (countOut).
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EEL4712T1Fall09 - EEL 4712 Digital Design Test 1 Fall...

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