EEL4712T1Fall10 - EEL 4712 Digital Design Test 1 Fall...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
EEL 4712 – Digital Design Test 1 – Fall Semester 2010 Name ___________________________________ 1 IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. Also, as always, the best answer gets the most points. 1. VHDL specification. Complete the VHDL specification (below and on the next page) for the following circuit: Notes: REG is an 8-bit storage register with a synchronous CLR and synchronous LD inputs (LD has priority over CLR). There are eight 2-to-1 MUX’s. INCR functions as follows: If inc = 0, F <= X, If inc = 1, F <= X + 1 (i.e., increment X). All signals are active high. (a) Complete the following Entity declaration for the Prob1 Module: (3 pts) LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; ENTITY Prob1 IS -- Declare ZOut to be an OUT signal type. PORT( END Prob1; (b) On the next page, complete the architecture section to specify the behavior of the Prob1 Module in behavioral VHDL. (20 pts) DATA CLR Q LD 8 8 0 1 2-to-1 MUX’s S INCR X F 8 8 inc CLR LD CLOCK InData SEL EN ZOut REG Prob1 Module 8 Z 23 pts.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EEL 4712 – Digital Design Test 1 – Fall Semester 2010 Name ___________________________________ 2 Notes: Follow exactly the requirements below Every statement must be inside a PROCESS statement (you can use any number of PROCESS statements). Hint: CASE and IF statements can help to make your code more structured. ARCHITECTURE behaviorArch OF Prob1 IS SIGNAL BEGIN PROCESS BEGIN -- You must use a WAIT UNTIL statement to specify the component REG END behaviorArch;
Background image of page 2
EEL 4712 – Digital Design Test 1 – Fall Semester 2010 Name ___________________________________ 3 2. VHDL analysis: timing diagram Shown below is the VHDL specification of a circuit. Analyze the VHDL code and complete the timing diagrams on the next page. ENTITY Prob2 IS PORT ( Clock, Resetn, X, R : IN STD_LOGIC ; Q, Y, Z : OUT STD_LOGIC ) ; END Prob2 ; ARCHITECTURE Behavior OF Prob2 IS SIGNAL tsig : STD_LOGIC_Vector (1 DOWNTO 0); BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN tsig <= "00" ; Q <= ‘0’; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE tsig IS WHEN "00" => IF X = '0' THEN tsig <= "01"; ELSE tsig <= "11"; END IF ; WHEN "01" => IF R = '1' THEN tsig <= "00" ; ELSE tsig <= "11" ; Q <= '1'; END IF ; WHEN "11" => tsig <= "01" ; WHEN OTHERS => tsig <= "00"; END CASE ; END IF ; END PROCESS ; PROCESS (tsig, R)
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 11

EEL4712T1Fall10 - EEL 4712 Digital Design Test 1 Fall...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online